Inventor · disambiguated record
Ali Vahidsafa
Also filed as: VAHIDSAFA ALI
34 granted patents·3 pending applications·107 citations·filing 1988–2023
95Inventor score
Top patents by PatentIndex Score
37 records- 0191US9026705B2Interrupt processing unit for preventing interrupt lossFEEHRER JOHN R·Filed 2012·Granted May 5, 2015·25 cites·13 claims
- 0286US11263012B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2020·Granted Mar 1, 2022·2 cites·20 claims
- 0385US10528351B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2017·Granted Jan 7, 2020·3 cites·20 claims
- 0483US8726114B1Testing of SRAMSORACLE INT CORP·Filed 2012·Granted May 13, 2014·9 cites·20 claims
- 0579US12277041B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2023·Granted Apr 15, 2025·0 cites·20 claims
- 0679US9509317B2Rotational synchronizer circuit for metastablity resolutionORACLE INT CORP·Filed 2013·Granted Nov 29, 2016·5 cites·20 claims
- 0778US9710273B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2014·Granted Jul 18, 2017·3 cites·20 claims
- 0875US10248520B2High speed functional test vectors in low power test conditions of a digital integrated circuitORACLE INT CORP·Filed 2016·Granted Apr 2, 2019·2 cites·18 claims
- 0974US11709742B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2022·Granted Jul 25, 2023·0 cites·20 claims
- 1073US8839025B2Systems and methods for retiring and unretiring cache linesSIVARAMAKRISHNAN RAMASWAMY·Filed 2011·Granted Sep 16, 2014·3 cites·20 claims
- 1172US9746876B2Drift compensation for a real time clock circuitORACLE INT CORP·Filed 2015·Granted Aug 29, 2017·2 cites·14 claims
- 1271US9218018B2Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domainVAHIDSAFA ALI·Filed 2012·Granted Dec 22, 2015·3 cites·12 claims
- 1367US9015460B2Hybrid hardwired/programmable reset sequence controllerVAHIDSAFA ALI·Filed 2012·Granted Apr 21, 2015·2 cites·20 claims
- 1466US9645903B2Managing failed memory modulesORACLE INT CORP·Filed 2015·Granted May 9, 2017·1 cites·18 claims
- 1566US9632141B2Simultaneous transition testing of different clock domains in a digital integrated circuitORACLE INT CORP·Filed 2014·Granted Apr 25, 2017·2 cites·20 claims
- 1666US8729947B2Wide-range glitch-free asynchronous clock switchHWANG CHANGKU·Filed 2012·Granted May 20, 2014·4 cites·19 claims
- 1766US4920485AMethod and apparatus for arbitration and serialization in a multiprocessor systemAMDAHL CORP·Filed 1988·Granted Apr 24, 1990·36 cites·9 claims
- 1865US9323600B2Systems and methods for retiring and unretiring cache linesORACLE INT CORP·Filed 2014·Granted Apr 26, 2016·1 cites·16 claims
- 1962US10467139B2Fault-tolerant cache coherence over a lossy networkORACLE INT CORP·Filed 2017·Granted Nov 5, 2019·1 cites·18 claims
- 2053US8943375B2Combo static flop with full testMASLEID ROBERT P·Filed 2012·Granted Jan 27, 2015·1 cites·23 claims
- 2151US9404967B2Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuitORACLE INT CORP·Filed 2014·Granted Aug 2, 2016·0 cites·20 claims
- 2250US9460013B2Method and system for removal of a cache agentORACLE INT CORP·Filed 2014·Granted Oct 4, 2016·0 cites·20 claims
- 2349US9569322B2Memory migration in presence of live memory trafficORACLE INT CORP·Filed 2015·Granted Feb 14, 2017·0 cites·20 claims
- 2448US9355211B2Unified tool for automatic design constraints generation and verificationORACLE INT CORP·Filed 2014·Granted May 31, 2016·0 cites·20 claims
- 2547US8972767B2Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time referenceORACLE INT CORP·Filed 2012·Granted Mar 3, 2015·0 cites·17 claims
- 2645US10656205B2Narrow-parallel scan-based device testingORACLE INT CORP·Filed 2018·Granted May 19, 2020·0 cites·18 claims
- 2745US8904254B2Combo dynamic flop with scanORACLE INT CORP·Filed 2012·Granted Dec 2, 2014·0 cites·14 claims
- 2845US8181073B2SRAM macro test flopVAHIDSAFA ALI·Filed 2009·Granted May 15, 2012·2 cites·17 claims
- 2944US10073139B2Cycle deterministic functional testing of a chip with asynchronous clock domainsORACLE INT CORP·Filed 2014·Granted Sep 11, 2018·0 cites·22 claims
- 3043US8990606B2Constant frequency architectural timer in a dynamic clock domainTURULLOLS SEBASTIAN·Filed 2012·Granted Mar 24, 2015·0 cites·18 claims
- 3141US2004148497A1Method and apparatus for determining an early reifetch address of a mispredicted conditional branch instruction in an out of order multi-issue processorVAHIDSAFA ALI·Filed 2003·Application pending·0 cites
- 3241US2004044881A1Method and system for early speculative store-load bypassSUN MICROSYSTEMS INC·Filed 2002·Application pending·0 cites
- 3339US10452547B2Fault-tolerant cache coherence over a lossy networkORACLE INT CORP·Filed 2017·Granted Oct 22, 2019·0 cites·15 claims
- 3439US10007629B2Inter-processor bus link and switch chip failure recoveryORACLE INT CORP·Filed 2015·Granted Jun 26, 2018·0 cites·20 claims
- 3539US9864604B2Distributed mechanism for clock and reset control in a microprocessorORACLE INT CORP·Filed 2015·Granted Jan 9, 2018·0 cites·18 claims
- 3639US2012218034A1Voltage calibration method and apparatusTURULLOLS SEBASTIAN·Filed 2011·Application pending·0 cites
- 3736US9052911B2Mechanism for consistent core hang detection in a a processor coreVAHIDSAFA ALI·Filed 2012·Granted Jun 9, 2015·0 cites·20 claims
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