Inventor · disambiguated record
Shu-Yi Ying
Also filed as: YING SHU-YI
13 granted patents·2 pending applications·40 citations·filing 2008–2024
89Inventor score
Top patents by PatentIndex Score
15 records- 0193US10402529B2Method and layout of an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 3, 2019·10 cites·20 claims
- 0291US11341308B2Method and layout of an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted May 24, 2022·2 cites·20 claims
- 0391US10936780B2Method and layout of an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 2, 2021·6 cites·20 claims
- 0491US10872190B2Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 22, 2020·5 cites·20 claims
- 0582US2024386180A1Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0680US12412019B2Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 9, 2025·0 cites·20 claims
- 0780US9275186B2Optimization for circuit migrationTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 1, 2016·5 cites·17 claims
- 0876US11714947B2Method and layout of an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 1, 2023·0 cites·20 claims
- 0974US10331838B2Semiconductor device with fill cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 25, 2019·2 cites·20 claims
- 1071US11615227B2Method and system for latch-up preventionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 28, 2023·0 cites·20 claims
- 1171US9672315B2Optimization for circuit migrationLU LEE-CHUNG·Filed 2010·Granted Jun 6, 2017·3 cites·20 claims
- 1271US2021374317A1Method of generating layout diagram including dummy pattern conversion and system of generating sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Application pending·0 cites
- 1365US11087063B2Method of generating layout diagram including dummy pattern conversion and system of generating sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 10, 2021·0 cites·20 claims
- 1464US7746142B2Circuit and method for clock skew compensation in voltage scalingTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Jun 29, 2010·5 cites·19 claims
- 1563US8232824B2Clock circuit and method for pulsed latch circuitsWANG CHUNG-HSING·Filed 2010·Granted Jul 31, 2012·2 cites·19 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →