Inventor · disambiguated record
Roden R. Topacio
Also filed as: TOPACIO III RODEN R · TOPACIO RODEN · TOPACIO RODEN R
37 granted patents·16 pending applications·235 citations·filing 2006–2023
97Inventor score
Files withTOPACIO RODEN R17ATI TECHNOLOGIES ULC15TOPACIO RODEN9ADVANCED MICRO DEVICES INC3ATI TECHNOLOGIES INC2
Top patents by PatentIndex Score
53 records- 0195US7670939B2Semiconductor chip bump connection apparatus and methodATI TECHNOLOGIES ULC·Filed 2008·Granted Mar 2, 2010·67 cites·16 claims
- 0294US8647974B2Method of fabricating a semiconductor chip with supportive terminal padTOPACIO RODEN R·Filed 2011·Granted Feb 11, 2014·22 cites·24 claims
- 0394US8227926B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2009·Granted Jul 24, 2012·28 cites·27 claims
- 0489US8299632B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2011·Granted Oct 30, 2012·9 cites·19 claims
- 0588US8120170B2Integrated package circuit with stiffenerMCLELLAN NEIL R·Filed 2008·Granted Feb 21, 2012·13 cites·16 claims
- 0686US11942405B2Semiconductor package assembly using a passive device as a standoffATI TECHNOLOGIES ULC·Filed 2021·Granted Mar 26, 2024·1 cites·19 claims
- 0786US9059159B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2013·Granted Jun 16, 2015·6 cites·15 claims
- 0886US8847383B2Integrated circuit package strip with stiffenerMCLELLAN NEIL R·Filed 2012·Granted Sep 30, 2014·7 cites·11 claims
- 0986US8298945B2Method of manufacturing substrates having asymmetric buildup layersLEUNG ANDREW·Filed 2011·Granted Oct 30, 2012·9 cites·14 claims
- 1082US7985621B2Method and apparatus for making semiconductor packagesATI TECHNOLOGIES ULC·Filed 2006·Granted Jul 26, 2011·8 cites·36 claims
- 1182US7888259B2Integrated circuit package employing predetermined three-dimensional solder pad surface and method for making sameATI TECHNOLOGIES ULC·Filed 2008·Granted Feb 15, 2011·11 cites·8 claims
- 1281US9318457B2Methods of fabricating semiconductor chip solder structuresTOPACIO RODEN R·Filed 2015·Granted Apr 19, 2016·3 cites·20 claims
- 1380US9209106B2Thermal management circuit board for stacked semiconductor chip deviceSHI XIAO LING·Filed 2012·Granted Dec 8, 2015·10 cites·28 claims
- 1480US7994044B2Semiconductor chip with contoured solder structure openingATI TECHNOLOGIES ULC·Filed 2009·Granted Aug 9, 2011·8 cites·20 claims
- 1578US9035471B2Routing layer for mitigating stress in a semiconductor dieATI TECHNOLOGIES ULC·Filed 2014·Granted May 19, 2015·3 cites·16 claims
- 1677US8664777B2Routing layer for mitigating stress in a semiconductor dieATI TECHNOLOGIES ULC·Filed 2012·Granted Mar 4, 2014·3 cites·16 claims
- 1775US11335659B2Semiconductor chip with patterned underbump metallization and polymer filmATI TECHNOLOGIES ULC·Filed 2016·Granted May 17, 2022·2 cites·20 claims
- 1871US8637983B2Face-to-face (F2F) hybrid structure for an integrated circuitMARTINEZ LIANE·Filed 2008·Granted Jan 28, 2014·6 cites·13 claims
- 1969US9576923B2Semiconductor chip with patterned underbump metallization and polymer filmTOPACIO RODEN R·Filed 2014·Granted Feb 21, 2017·2 cites·15 claims
- 2069US8313984B2Die substrate with reinforcement structureTOPACIO RODEN·Filed 2008·Granted Nov 20, 2012·4 cites·18 claims
- 2166US7906424B2Conductor bump method and apparatusADVANCED MICRO DEVICES INC·Filed 2007·Granted Mar 15, 2011·3 cites·18 claims
- 2265US8378471B2Semiconductor chip bump connection apparatus and methodATI TECHNOLOGIES ULC·Filed 2010·Granted Feb 19, 2013·1 cites·16 claims
- 2364US9728518B2Interconnect etch with polymer layer edge protectionTOPACIO RODEN R·Filed 2014·Granted Aug 8, 2017·1 cites·19 claims
- 2464US8389340B2Methods of forming semiconductor chip underfill anchorsTOPACIO RODEN R·Filed 2011·Granted Mar 5, 2013·1 cites·14 claims
- 2563US8058108B2Methods of forming semiconductor chip underfill anchorsTOPACIO RODEN R·Filed 2010·Granted Nov 15, 2011·1 cites·10 claims
- 2663US7973408B2Semiconductor chip passivation structures and methods of making the sameATI TECHNOLOGIES ULC·Filed 2010·Granted Jul 5, 2011·1 cites·20 claims
- 2762US10431533B2Circuit board with constrained solder interconnect padsTOPACIO RODEN·Filed 2014·Granted Oct 1, 2019·1 cites·20 claims
- 2861US12148715B2Electronic device including a substrate, a structure, and an adhesive and a process of forming the sameATI TECHNOLOGIES ULC·Filed 2021·Granted Nov 19, 2024·0 cites·16 claims
- 2961US8927344B2Die substrate with reinforcement structureTOPACIO RODEN·Filed 2012·Granted Jan 6, 2015·1 cites·20 claims
- 3061US8772083B2Solder mask with anchor structuresLEUNG ANDREW K W·Filed 2011·Granted Jul 8, 2014·2 cites·12 claims
- 3160US7790501B2Semiconductor chip passivation structures and methods of making the sameATI TECHNOLOGIES ULC·Filed 2008·Granted Sep 7, 2010·1 cites·16 claims
- 3256US2024332098A1Lid assembly for a chip packageADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 3354US10403589B2Interconnect etch with polymer layer edge protectionTOPACIO RODEN R·Filed 2017·Granted Sep 3, 2019·0 cites·14 claims
- 3454US8633599B2Semiconductor chip with underfill anchorsTOPACIO RODEN·Filed 2013·Granted Jan 21, 2014·0 cites·18 claims
- 3554US2024038703A1Semiconductor assembly including multiple solder masksATI TECHNOLOGIES ULC·Filed 2022·Application pending·0 cites
- 3653US11315883B2Integrated circuit product customizations for identification code visibilityADVANCED MICRO DEVICES INC·Filed 2019·Granted Apr 26, 2022·0 cites·21 claims
- 3753US8642463B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2012·Granted Feb 4, 2014·0 cites·3 claims
- 3850US9142520B2Methods of fabricating semiconductor chip solder structuresTOPACIO RODEN R·Filed 2011·Granted Sep 22, 2015·0 cites·16 claims
- 3950US2011024898A1Method of manufacturing substrates having asymmetric buildup layersATI TECHNOLOGIES ULC·Filed 2009·Application pending·0 cites
- 4049US2008054490A1Flip-Chip Ball Grid Array Strip and PackageATI TECHNOLOGIES INC·Filed 2006·Application pending·0 cites
- 4147US8294266B2Conductor bump method and apparatusTOPACIO RODEN R·Filed 2011·Granted Oct 23, 2012·0 cites·15 claims
- 4246US2011057307A1Semiconductor Chip with Stair Arrangement Bump StructuresTOPACIO RODEN R·Filed 2009·Application pending·0 cites
- 4346US2011100692A1Circuit Board with Variable Topography Solder InterconnectsTOPACIO RODEN·Filed 2009·Application pending·0 cites
- 4445US2008099910A1Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and StripATI TECHNOLOGIES INC·Filed 2007·Application pending·0 cites
- 4543US2009032941A1Under Bump Routing Layer Method and ApparatusMCLELLAN NEIL·Filed 2007·Application pending·0 cites
- 4643US2008169555A1Anchor structure for an integrated circuitATI TECHNOLOGIES ULC·Filed 2007·Application pending·0 cites
- 4742US2010102457A1Hybrid Semiconductor Chip PackageTOPACIO RODEN R·Filed 2008·Application pending·0 cites
- 4842US2011222256A1Circuit board with anchored underfillTOPACIO RODEN R·Filed 2010·Application pending·0 cites
- 4940US2013256871A1Semiconductor chip device with fragmented solder structure padsTOPACIO RODEN R·Filed 2012·Application pending·0 cites
- 5039US2012261812A1Semiconductor chip with patterned underbump metallizationTOPACIO RODEN R·Filed 2011·Application pending·0 cites
Showing the top 50 of 53 patent records by PatentIndex Score.
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