Inventor · disambiguated record
Eddy Pramono
Also filed as: PRAMONO EDDY
11 granted patents·74 citations·filing 2003–2014
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0189US8103996B2Method and apparatus for thermal analysis of through-silicon via (TSV)KARIAT VINOD·Filed 2009·Granted Jan 24, 2012·21 cites·38 claims
- 0284US8504958B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2011·Granted Aug 6, 2013·8 cites·19 claims
- 0383US8104006B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2008·Granted Jan 24, 2012·13 cites·29 claims
- 0479US8104007B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2008·Granted Jan 24, 2012·9 cites·27 claims
- 0576US8543952B2Method and apparatus for thermal analysis of through-silicon via (TSV)KARIAT VINOD·Filed 2011·Granted Sep 24, 2013·4 cites·20 claims
- 0676US8201113B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2008·Granted Jun 12, 2012·7 cites·20 claims
- 0774US9582626B1Using waveform propagation for accurate delay calculationCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Feb 28, 2017·4 cites·23 claims
- 0862US8566760B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2012·Granted Oct 22, 2013·1 cites·18 claims
- 0955US6925619B2IC conductor capacitance estimation methodCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 2, 2005·5 cites·26 claims
- 1050US8694934B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2012·Granted Apr 8, 2014·0 cites·18 claims
- 1150US7024644B2IC signal path resistance estimation methodCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Apr 4, 2006·2 cites·13 claims
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