Inventor · disambiguated record
Liji Gopalakrishnan
Also filed as: GOPALAKRISHNAN LIJI
46 granted patents·7 pending applications·79 citations·filing 2012–2025
97Inventor score
Top patents by PatentIndex Score
53 records- 0196US11803489B2Calibration protocol for command and address bus voltage reference in low-swing single-ended signalingRAMBUS INC·Filed 2022·Granted Oct 31, 2023·3 cites·17 claims
- 0296US11327831B2Energy-efficient error-correction-detection storageRAMBUS INC·Filed 2020·Granted May 10, 2022·4 cites·20 claims
- 0395US11049546B2Memory component with command-triggered data clock distributionRAMBUS INC·Filed 2020·Granted Jun 29, 2021·3 cites·20 claims
- 0493US9098281B2Power-management for integrated circuitsSHAEFFER IAN·Filed 2012·Granted Aug 4, 2015·11 cites·20 claims
- 0592US11972121B2Load-reduced DRAM stackRAMBUS INC·Filed 2021·Granted Apr 30, 2024·2 cites·20 claims
- 0691US9275699B2Memory with alternative command interfacesRAMBUS INC·Filed 2013·Granted Mar 1, 2016·10 cites·23 claims
- 0790US10613924B2Energy-efficient error-correction-detection storageRAMBUS INC·Filed 2018·Granted Apr 7, 2020·4 cites·19 claims
- 0890US9098209B2Communication via a memory interfaceRAMBUS INC·Filed 2013·Granted Aug 4, 2015·11 cites·17 claims
- 0990US2025356905A1Command-triggered data clock distributionRAMBUS INC·Filed 2025·Application pending·0 cites
- 1086US9704560B2Memory component with staggered power-down exitRAMBUS INC·Filed 2016·Granted Jul 11, 2017·4 cites·20 claims
- 1185US12411729B2Energy-efficient error-correction-detection storageRAMBUS INC·Filed 2024·Granted Sep 9, 2025·0 cites·17 claims
- 1285US12347479B2Command-triggered data clock distribution modeRAMBUS INC·Filed 2024·Granted Jul 1, 2025·0 cites·21 claims
- 1385US11842761B2Memory system with multiple open rows per bankRAMBUS INC·Filed 2021·Granted Dec 12, 2023·1 cites·20 claims
- 1485US2025364033A1Memory system with multiple open rows per bankRAMBUS INC·Filed 2025·Application pending·0 cites
- 1583US10089256B2Calibration protocol for command and address bus voltage reference in low-swing single-ended signalingRAMBUS INC·Filed 2017·Granted Oct 2, 2018·2 cites·19 claims
- 1683US2025036581A1Flash memory device having a calibration modeRAMBUS INC·Filed 2024·Application pending·0 cites
- 1783US2025370626A1Partial array refresh timingRAMBUS INC·Filed 2025·Application pending·0 cites
- 1882US12347480B2Memory system with multiple open rows per bankRAMBUS INC·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 1982US12072817B2Flash memory device having a calibration modeRAMBUS INC·Filed 2023·Granted Aug 27, 2024·0 cites·20 claims
- 2081US11955161B2Command-triggered data clock distribution modeRAMBUS INC·Filed 2023·Granted Apr 9, 2024·0 cites·21 claims
- 2180US12498864B2Load-reduced DRAM stackRAMBUS INC·Filed 2024·Granted Dec 16, 2025·0 cites·21 claims
- 2280US12346567B2Partial array refresh timingRAMBUS INC·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 2380US12050513B2Energy-efficient error-correction-detection storageRAMBUS INC·Filed 2023·Granted Jul 30, 2024·0 cites·20 claims
- 2480US11829308B2Flash memory device having a calibration modeRAMBUS INC·Filed 2022·Granted Nov 28, 2023·0 cites·20 claims
- 2579US9734112B2Memory with alternative command interfacesRAMBUS INC·Filed 2016·Granted Aug 15, 2017·3 cites·17 claims
- 2678US10747703B2Memory with alternative command interfacesRAMBUS INC·Filed 2019·Granted Aug 18, 2020·2 cites·20 claims
- 2778US9287003B2Multi-cycle write levelingRAMBUS INC·Filed 2014·Granted Mar 15, 2016·7 cites·20 claims
- 2877US11921650B2Dedicated cache-related block transfer in a memory systemRAMBUS INC·Filed 2023·Granted Mar 5, 2024·0 cites·20 claims
- 2976US11782863B2Memory module with configurable command bufferRAMBUS INC·Filed 2022·Granted Oct 10, 2023·0 cites·19 claims
- 3076US11675657B2Energy-efficient error-correction-detection storageRAMBUS INC·Filed 2022·Granted Jun 13, 2023·0 cites·20 claims
- 3176US11587605B2Command-triggered data clock distributionRAMBUS INC·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 3276US2024152470A1Dram interface mode with interruptible internal transfer operationRAMBUS INC·Filed 2023·Application pending·0 cites
- 3374US8990490B2Memory controller with reconfigurable hardwareRAMBUS INC·Filed 2012·Granted Mar 24, 2015·8 cites·31 claims
- 3473US11829307B2DRAM interface mode with interruptible internal transfer operationRAMBUS INC·Filed 2022·Granted Nov 28, 2023·0 cites·20 claims
- 3570US11599483B2Dedicated cache-related block transfer in a memory systemRAMBUS INC·Filed 2022·Granted Mar 7, 2023·0 cites·20 claims
- 3670US11372795B2Memory with alternative command interfacesRAMBUS INC·Filed 2020·Granted Jun 28, 2022·0 cites·20 claims
- 3770US11372784B2Calibration protocol for command and address bus voltage reference in low-swing single-ended signalingRAMBUS INC·Filed 2019·Granted Jun 28, 2022·0 cites·17 claims
- 3870US2025218476A1Hierarchical bank group timingRAMBUS INC·Filed 2025·Application pending·0 cites
- 3969US11868619B2Partial array refresh timingRAMBUS INC·Filed 2020·Granted Jan 9, 2024·0 cites·20 claims
- 4068US10665289B2Memory component with independently enabled data and command interfacesRAMBUS INC·Filed 2018·Granted May 26, 2020·0 cites·20 claims
- 4167US11114150B2Memory system with multiple open rows per bankRAMBUS INC·Filed 2020·Granted Sep 7, 2021·0 cites·20 claims
- 4266US11232047B2Dedicated cache-related block transfer in a memory systemRAMBUS INC·Filed 2020·Granted Jan 25, 2022·0 cites·20 claims
- 4366US10509741B2Calibration protocol for command and address bus voltage reference in low-swing single-ended signalingRAMBUS INC·Filed 2018·Granted Dec 17, 2019·0 cites·20 claims
- 4465US11226909B2DRAM interface mode with interruptible internal transfer operationRAMBUS INC·Filed 2019·Granted Jan 18, 2022·0 cites·20 claims
- 4564US8938578B2Memory device with multi-mode deserializerRAMBUS INC·Filed 2013·Granted Jan 20, 2015·4 cites·18 claims
- 4659US9715467B2Calibration protocol for command and address bus voltage reference in low-swing single-ended signalingRAMBUS INC·Filed 2013·Granted Jul 25, 2017·0 cites·20 claims
- 4757US12230355B2Hierarchical bank group timingRAMBUS INC·Filed 2020·Granted Feb 18, 2025·0 cites·14 claims
- 4856US10026466B2Staggered exit from memory power-downRAMBUS INC·Filed 2017·Granted Jul 17, 2018·0 cites·20 claims
- 4953US11526632B2Securing address information in a memory controllerRAMBUS INC·Filed 2020·Granted Dec 13, 2022·0 cites·20 claims
- 5053US9430027B2Power-management for integrated circuitsRAMBUS INC·Filed 2015·Granted Aug 30, 2016·0 cites·20 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
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