Inventor · disambiguated record
Gunjan H. Pandya
Also filed as: PANDYA GUNJAN · PANDYA GUNJAN H
12 granted patents·1 pending application·81 citations·filing 2004–2017
89Inventor score
Top patents by PatentIndex Score
13 records- 0193US9378788B2Negative bitline write assist circuit and method for operating the sameKOLAR PRAMOD·Filed 2012·Granted Jun 28, 2016·19 cites·23 claims
- 0289US9208853B2Dual-port static random access memory (SRAM)INTEL CORP·Filed 2013·Granted Dec 8, 2015·12 cites·16 claims
- 0380US9818460B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2016·Granted Nov 14, 2017·4 cites·23 claims
- 0478US8406073B1Hierarchical DRAM sensingSOMASEKHAR DINESH·Filed 2010·Granted Mar 26, 2013·8 cites·19 claims
- 0572US6985380B2SRAM with forward body biasing to improve read cell stabilityINTEL CORP·Filed 2004·Granted Jan 10, 2006·18 cites·12 claims
- 0669US7385865B2Memory circuitINTEL CORP·Filed 2004·Granted Jun 10, 2008·16 cites·5 claims
- 0750US8868836B2Reducing minimum operating voltage through hybrid cache designKHELLAH MUHAMMAD M·Filed 2007·Granted Oct 21, 2014·2 cites·19 claims
- 0849US10902893B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2017·Granted Jan 26, 2021·0 cites·21 claims
- 0949US10818326B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2017·Granted Oct 27, 2020·0 cites·22 claims
- 1048US2011161783A1Method and apparatus on direct matching of cache tags coded with error correcting codes (ecc)SOMASEKHAR DINESH·Filed 2009·Application pending·0 cites
- 1141US9607687B2Dual-port static random access memory (SRAM)INTEL CORP·Filed 2015·Granted Mar 28, 2017·0 cites·22 claims
- 1241US8982659B2Bitline floating during non-access mode for memory arraysCHANG TSUNG-YUNG·Filed 2009·Granted Mar 17, 2015·2 cites·20 claims
- 1332US9812189B2Read and write apparatus and method for a dual port memoryINTEL CORP·Filed 2015·Granted Nov 7, 2017·0 cites·19 claims
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