Inventor · disambiguated record
Yi-Lin Chuang
Also filed as: CHUANG YI-LIN
49 granted patents·8 pending applications·137 citations·filing 2012–2025
98Inventor score
Top patents by PatentIndex Score
57 records- 0196US10678973B2Machine-learning design enablement platformTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 9, 2020·13 cites·20 claims
- 0295US11816417B2Rule check violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 14, 2023·3 cites·20 claims
- 0395US11562118B2Hard-to-fix (HTF) design rule check (DRC) violations predictionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 24, 2023·3 cites·20 claims
- 0494US11709987B2Method and system for generating layout design of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jul 25, 2023·4 cites·20 claims
- 0594US11443097B2System and method for diagnosing design rule check violationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 13, 2022·3 cites·16 claims
- 0694US11093681B2Method and system for generating layout design of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 17, 2021·5 cites·17 claims
- 0794US10162925B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 25, 2018·10 cites·20 claims
- 0893US11928415B2Hard-to-fix (HTF) design rule check (DRC) violations predictionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 12, 2024·1 cites·20 claims
- 0993US11900037B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 13, 2024·2 cites·20 claims
- 1093US11481536B2Method and system for fixing violation of layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Oct 25, 2022·5 cites·20 claims
- 1193US11443096B2Method for optimizing floor plan for an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 13, 2022·3 cites·20 claims
- 1293US11347920B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 31, 2022·3 cites·20 claims
- 1393US11087066B2Static voltage drop (SIR) violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 10, 2021·3 cites·20 claims
- 1493US8887117B1Register clustering for clock network topology generationTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 11, 2014·18 cites·14 claims
- 1591US10810346B2Static voltage drop (SIR) violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 20, 2020·10 cites·20 claims
- 1689US12039249B2System and method for diagnosing design rule check violationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 16, 2024·1 cites·19 claims
- 1789US11017149B2Machine-learning design enablement platformTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 25, 2021·2 cites·20 claims
- 1889US10943049B2Rule check violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 9, 2021·8 cites·17 claims
- 1986US2025087580A1Method of forming a semiconductor device with inter-layer vias and semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2085US9679840B2Method for layout design and structure with inter-layer viasTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 13, 2017·5 cites·20 claims
- 2184US11604917B2Static voltage drop (SIR) violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 14, 2023·1 cites·20 claims
- 2284US11568119B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 31, 2023·1 cites·20 claims
- 2383US12299376B2Hard-to-fix (HTF) design rule check (DRC) violations predictionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted May 13, 2025·0 cites·20 claims
- 2483US10922466B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Feb 16, 2021·2 cites·20 claims
- 2583US8701070B2Group bounding box region-constrained placement for integrated circuit designCHUANG YI-LIN·Filed 2012·Granted Apr 15, 2014·9 cites·20 claims
- 2683US2025258990A1Hard-to-fix (htf) design rule check (drc) violations predictionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2783US2025291989A1Circuit Synthesis Optimization for Implements on Integrated CircuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2882US10268795B2Method and system for timing optimization with detour predictionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·6 cites·17 claims
- 2982US9275176B2Register clustering for clock network topology generationTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 1, 2016·5 cites·14 claims
- 3081US12340158B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jun 24, 2025·0 cites·20 claims
- 3181US2025284873A1Post-Routing Congestion OptimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3279US12039251B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 16, 2024·0 cites·20 claims
- 3378US12242788B2Method and system for generating layout design of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 3477US12321682B2Post-routing congestion optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 3577US8898608B1Method for displaying timing information of an integrated circuit floorplanTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 25, 2014·3 cites·20 claims
- 3677US2024330563A1System and method for diagnosing design rule check violationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 3776US12106034B2Rule check violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 1, 2024·0 cites·20 claims
- 3876US12099793B2Rule check violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 24, 2024·0 cites·20 claims
- 3976US2024104285A1Method for optimizing floor plan for an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 4076US2024394460A1Rule check violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4175US12154851B2Method of forming a semiconductor device with inter-layer viasTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 26, 2024·0 cites·20 claims
- 4274US2025156621A1Method and system for generating layout design of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4373US11893334B2Method for optimizing floor plan for an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 6, 2024·0 cites·20 claims
- 4473US11853675B2Method for optimizing floor plan for an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 26, 2023·0 cites·20 claims
- 4571US8863062B2Methods and apparatus for floorplanning and routing co-designCHUANG YI-LIN·Filed 2012·Granted Oct 14, 2014·3 cites·20 claims
- 4671US8707238B2Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designsCHUANG YI-LIN·Filed 2012·Granted Apr 22, 2014·3 cites·19 claims
- 4770US11114376B2System for layout design of structure with inter layer viasTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 7, 2021·0 cites·20 claims
- 4869US11853681B2Post-routing congestion optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 26, 2023·0 cites·20 claims
- 4967US12019971B2Static voltage drop (SIR) violation prediction systems and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 25, 2024·0 cites·20 claims
- 5066US12216980B2Method and system for fixing violation of layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 4, 2025·0 cites·20 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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