Inventor

DOYLE BRIAN S

US301 patents

⚠️ This page may combine multiple inventors who share the name “DOYLE BRIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOYLE BRIAN S

INTEL CORP

Unity beta ratio tri-gate transistor static random access memory (SRAM)

Strained transistor integration for CMOS

Self-aligned contacts for transistors

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers

Tri-gate devices and methods of fabrication

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Tri-gate transistors and methods to fabricate same

Nonplanar device with stress incorporation layer and method of fabrication

Nonplanar transistors with metal gate electrodes

Independently accessed double-gate and tri-gate transistors in same process flow

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Multi-gate carbon nano-tube transistors

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Tri-gate devices and methods of fabrication

Transistor structure and method of fabrication

Semiconductor transistor having a backfilled channel material

Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel

Method of delaminating a thin film using non-thermal techniques

Methodology for control of short channel effects in MOS transistors

Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering

Method of increasing the mobility of MOS transistors by use of localized stress regions

Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition

Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer

Block contact architectures for nanoscale channel transistors

Tri-gate patterning using dual layer gate stack

Methods for patterning a semiconductor film

Non-planar MOS structure with a strained channel region

Multigate device with recessed strain regions

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Method of ion implanting for tri-gate devices

Stacked multi-gate transistor design and method of fabrication

Nonplanar transistors with metal gate electrodes

Nonplanar transistors with metal gate electrodes

Method of forming a metal oxide dielectric

Block contact architectures for nanoscale channel transistors

Non-planar MOS structure with a strained channel region

Method and apparatus for improving stability of a 6T CMOS SRAM cell

Integrating n-type and p-type metal gate transistors

MOS transistor using mechanical stress to control short channel effects

Process to make complementary silicide metal gates for CMOS technology

Low temperature method of forming gate electrode and gate dielectric

Balancing energy barrier between states in perpendicular magnetic tunnel junctions

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

N-gate transistor

DIGITAL EQUIPMENT CORP

Method of controlling gate oxide thickness in the fabrication of semiconductor devices

Method of decreasing the field oxide etch rate in isolation technology