Inventor · disambiguated record
Sarathy Rajagopalan
Also filed as: RAJAGOPALAN SARATHY
10 granted patents·3 pending applications·145 citations·filing 1999–2019
89Inventor score
Top patents by PatentIndex Score
13 records- 0182US6441499B1Thin form factor flip chip ball grid arrayLSI LOGIC CORP·Filed 2000·Granted Aug 27, 2002·33 cites·7 claims
- 0277US6518161B1Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded dieLSI LOGIC CORP·Filed 2001·Granted Feb 11, 2003·26 cites·21 claims
- 0375US6825556B2Integrated circuit package design with non-orthogonal die cut outLSI LOGIC CORP·Filed 2002·Granted Nov 30, 2004·21 cites·7 claims
- 0475US6586825B1Dual chip in package with a wire bonded die mounted to a substrateLSI LOGIC CORP·Filed 2001·Granted Jul 1, 2003·23 cites·37 claims
- 0560US7041516B2Multi chip module assemblyLSI LOGIC CORP·Filed 2002·Granted May 9, 2006·7 cites·19 claims
- 0655US7352062B2Integrated circuit package designLSI LOGIC CORP·Filed 2004·Granted Apr 1, 2008·6 cites·20 claims
- 0755US6320127B1Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component packageLSI LOGIC CORP·Filed 1999·Granted Nov 20, 2001·21 cites·23 claims
- 0845US6465338B1Method of planarizing die solder balls by employing a die's weightLSI LOGIC CORP·Filed 2000·Granted Oct 15, 2002·1 cites·1 claims
- 0941US11625727B2Dispute resolution system interfacePAYPAL INC·Filed 2019·Granted Apr 11, 2023·0 cites·20 claims
- 1039US2006128072A1Method of protecting fuses in an integrated circuit dieLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1137US2006131283A1Method and apparatus for forming angled vias in an integrated circuit package substrateLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1234US6962437B1Method and apparatus for thermal profiling of flip-chip packagesLSI LOGIC CORP·Filed 1999·Granted Nov 8, 2005·7 cites·6 claims
- 1334US2004099962A1Flip chip electrical test yields by countering substrate die area coplanarityFiled 2002·Application pending·0 cites
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