Inventor · disambiguated record
Todd A. Christensen
Also filed as: CHRISTENSEN TODD A · CHRISTENSEN TODD ALAN
101 granted patents·15 pending applications·1,498 citations·filing 1996–2021
99Inventor score
Top patents by PatentIndex Score
116 records- 0197US9455313B1High-density integrated circuit via capacitorIBM·Filed 2015·Granted Sep 27, 2016·21 cites·6 claims
- 0297US6774734B2Ring oscillator circuit for EDRAM/DRAM performance monitoringIBM·Filed 2002·Granted Aug 10, 2004·91 cites·13 claims
- 0396US8300450B2Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variationCHRISTENSEN TODD ALAN·Filed 2010·Granted Oct 30, 2012·41 cites·20 claims
- 0494US6492244B1Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devicesIBM·Filed 2001·Granted Dec 10, 2002·81 cites·10 claims
- 0593US6538522B1Method and ring oscillator for evaluating dynamic circuitsIBM·Filed 2001·Granted Mar 25, 2003·53 cites·20 claims
- 0692US8520429B2Data dependent SRAM write assistBEHRENDS DERICK G·Filed 2011·Granted Aug 27, 2013·18 cites·2 claims
- 0791US8754417B2Vertical stacking of field effect transistor structures for logic gatesCHRISTENSEN TODD ALAN·Filed 2012·Granted Jun 17, 2014·12 cites·5 claims
- 0891US6121659ABuried patterned conductor planes for semiconductor-on-insulator integrated circuitIBM·Filed 1998·Granted Sep 19, 2000·127 cites·17 claims
- 0991US5778243AMulti-threaded cell for a memoryIBM·Filed 1996·Granted Jul 7, 1998·211 cites·35 claims
- 1090US9058861B2Power management SRAM write bit line drive circuitIBM·Filed 2012·Granted Jun 16, 2015·13 cites·20 claims
- 1190US8578304B1Implementing mulitple mask lithography timing variation mitigationBEHRENDS DERICK G·Filed 2012·Granted Nov 5, 2013·7 cites·17 claims
- 1290US8531203B2Mask alignment, rotation and bias monitor utilizing threshold voltage dependenceCHRISTENSEN TODD A·Filed 2010·Granted Sep 10, 2013·14 cites·20 claims
- 1390US7727887B2Method for improved power distribution in a three dimensional vertical integrated circuitIBM·Filed 2007·Granted Jun 1, 2010·13 cites·18 claims
- 1490US6429099B1Implementing contacts for bodies of semiconductor-on-insulator transistorsIBM·Filed 2000·Granted Aug 6, 2002·41 cites·8 claims
- 1589US9455251B1Decoupling capacitor using finFET topologyIBM·Filed 2015·Granted Sep 27, 2016·6 cites·20 claims
- 1689US8159260B1Delay chain burn-in for increased repeatability of physically unclonable functionsBEHRENDS DERICK GARDNER·Filed 2010·Granted Apr 17, 2012·15 cites·13 claims
- 1789US6657886B1Split local and continuous bitline for fast domino read SRAMIBM·Filed 2002·Granted Dec 2, 2003·52 cites·11 claims
- 1889US6498057B1Method for implementing SOI transistor source connections using buried dual rail distributionIBM·Filed 2002·Granted Dec 24, 2002·47 cites·8 claims
- 1988US8842487B2Power management domino SRAM bit line discharge circuitIBM·Filed 2013·Granted Sep 23, 2014·9 cites·1 claims
- 2086US8105940B2Power distribution in a vertically integrated circuitCHRISTENSEN TODD ALAN·Filed 2010·Granted Jan 31, 2012·6 cites·20 claims
- 2186US7989918B2Implementing tamper evident and resistant detection through modulation of capacitanceIBM·Filed 2009·Granted Aug 2, 2011·13 cites·20 claims
- 2286US7414878B1Method for implementing domino SRAM leakage current reductionIBM·Filed 2007·Granted Aug 19, 2008·16 cites·9 claims
- 2385US6670716B2Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distributionIBM·Filed 2002·Granted Dec 30, 2003·34 cites·8 claims
- 2484US7723816B2Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chipsIBM·Filed 2008·Granted May 25, 2010·10 cites·12 claims
- 2584US7502276B1Method and apparatus for multi-word write in domino read SRAMsIBM·Filed 2008·Granted Mar 10, 2009·15 cites·1 claims
- 2684US6643804B1Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under testIBM·Filed 2000·Granted Nov 4, 2003·37 cites·31 claims
- 2783US7525367B2Method for implementing level shifter circuits for integrated circuitsIBM·Filed 2006·Granted Apr 28, 2009·12 cites·3 claims
- 2883US6287901B1Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistorsIBM·Filed 2000·Granted Sep 11, 2001·30 cites·8 claims
- 2983US5872697AIntegrated circuit having integral decoupling capacitorIBM·Filed 1996·Granted Feb 16, 1999·61 cites·19 claims
- 3082US9514841B1Implementing eFuse visual security of stored data using EDRAMIBM·Filed 2015·Granted Dec 6, 2016·4 cites·15 claims
- 3182US7924633B2Implementing boosted wordline voltage in memoriesIBM·Filed 2009·Granted Apr 12, 2011·13 cites·17 claims
- 3282US7817481B2Column selectable self-biasing virtual voltages for SRAM write assistIBM·Filed 2008·Granted Oct 19, 2010·13 cites·14 claims
- 3382US6645796B2Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devicesIBM·Filed 2001·Granted Nov 11, 2003·30 cites·8 claims
- 3481US6667518B2Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devicesIBM·Filed 2002·Granted Dec 23, 2003·26 cites·10 claims
- 3579US10381098B2Memory interface latch with integrated write-through and fence functionsIBM·Filed 2017·Granted Aug 13, 2019·2 cites·18 claims
- 3678US10229748B1Memory interface latch with integrated write-through functionIBM·Filed 2017·Granted Mar 12, 2019·4 cites·18 claims
- 3778US7609542B2Implementing enhanced SRAM read performance sort ring oscillator (PSRO)IBM·Filed 2007·Granted Oct 27, 2009·10 cites·19 claims
- 3877US7715221B2Apparatus for implementing domino SRAM leakage current reductionIBM·Filed 2008·Granted May 11, 2010·9 cites·9 claims
- 3976US9496326B1High-density integrated circuit via capacitorIBM·Filed 2015·Granted Nov 15, 2016·2 cites·12 claims
- 4076US8669800B2Implementing power saving self powering down latch structureBEHRENDS DERICK G·Filed 2012·Granted Mar 11, 2014·4 cites·20 claims
- 4175US7480170B1Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)IBM·Filed 2007·Granted Jan 20, 2009·9 cites·20 claims
- 4275US6901003B2Lower power and reduced device split local and continuous bitline for domino read SRAMsIBM·Filed 2003·Granted May 31, 2005·21 cites·20 claims
- 4375US5889306ABulk silicon voltage plane for SOI applicationsIBM·Filed 1997·Granted Mar 30, 1999·46 cites·23 claims
- 4474US7844869B2Implementing enhanced LBIST testing of paths including arraysIBM·Filed 2008·Granted Nov 30, 2010·7 cites·19 claims
- 4573US8172140B2Doped implant monitoring for microchip tamper detectionBARTLEY GERALD K·Filed 2008·Granted May 8, 2012·5 cites·20 claims
- 4673US7724586B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usageIBM·Filed 2008·Granted May 25, 2010·8 cites·18 claims
- 4773US7684263B2Method and circuit for implementing enhanced SRAM write and read performance ring oscillatorIBM·Filed 2008·Granted Mar 23, 2010·8 cites·16 claims
- 4872US9646712B1Implementing eFuse visual security of stored data using EDRAMIBM·Filed 2016·Granted May 9, 2017·2 cites·5 claims
- 4972US9082484B1Partial update in a ternary content addressable memoryIBM·Filed 2013·Granted Jul 14, 2015·2 cites·12 claims
- 5072US6528853B2Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistorsIBM·Filed 2001·Granted Mar 4, 2003·16 cites·2 claims
Showing the top 50 of 116 patent records by PatentIndex Score.
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