Inventor · disambiguated record
Xavier Van Ruymbeke
Also filed as: VAN RUYMBEKE XAVIER
9 granted patents·9 pending applications·87 citations·filing 2012–2025
86Inventor score
Top patents by PatentIndex Score
18 records- 0193US11210445B1System and method for interface protectionARTERIS INC·Filed 2020·Granted Dec 28, 2021·6 cites·20 claims
- 0293US9825779B2Network-on-chip (NoC) topology generationARTERIS INC·Filed 2015·Granted Nov 21, 2017·21 cites·14 claims
- 0391US8793644B2Display and automatic improvement of timing and area in a network-on-chipMICHEL DANIEL·Filed 2012·Granted Jul 29, 2014·47 cites·13 claims
- 0490US11847394B2System and method for using interface protection parametersARTERIS INC·Filed 2021·Granted Dec 19, 2023·2 cites·12 claims
- 0588US12237980B2Topology synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2021·Granted Feb 25, 2025·2 cites·15 claims
- 0688US10528421B2Protection scheme conversionARTERIS INC·Filed 2015·Granted Jan 7, 2020·9 cites·26 claims
- 0777US12340156B2System and method for using interface protection parametersARTERIS INC·Filed 2023·Granted Jun 24, 2025·0 cites·13 claims
- 0872US2025265404A1ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC)ARTERIS INC·Filed 2025·Application pending·0 cites
- 0962US2024403531A1Design tool for automated placement constraint generation, adapter insertion process, and local and global congestion captureARTERIS INC·Filed 2024·Application pending·0 cites
- 1060US2024404147A1System and method for generation of a network using physical awareness data from an image of a chip floorplanARTERIS INC·Filed 2024·Application pending·0 cites
- 1158US2025174294A1TOOL FOR FAULT DETECTION AND CLASSIFICATION IN DESIGN AND GENERATION OF NETWORK-ON-CHIP (NoCs)ARTERIS INC·Filed 2024·Application pending·0 cites
- 1258US2025117355A1SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs)ARTERIS INC·Filed 2024·Application pending·0 cites
- 1356US2025117566A1SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs) USING INCREMENTAL TOPOLOGY SYNTHESIS FOR OPTIMIZATION OF SWITCHESARTERIS INC·Filed 2024·Application pending·0 cites
- 1456US2024427978A1Tool for supporting use of regular network topologies in generating a network-on-chip topologyARTERIS INC·Filed 2024·Application pending·0 cites
- 1551US9098658B2Display and automatic improvement of timing and area in a network-on-chipQUALCOMM TECHNOLOGIES INC·Filed 2013·Granted Aug 4, 2015·0 cites·14 claims
- 1650US2024353813A1Process for generating physical implementation guidance during the synthesis of a network-on-chipARTERIS INC·Filed 2023·Application pending·0 cites
- 1750US2024243994A1System and method for deterministic and incremental physically-aware network-on-chip generationARTERIS INC·Filed 2023·Application pending·0 cites
- 1848US10489241B2Control and address redundancy in storage bufferARTERIS INC·Filed 2016·Granted Nov 26, 2019·0 cites·3 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →