Inventor · disambiguated record
Mark R. Hartoog
Also filed as: HARTOOG MARK · HARTOOG MARK R
11 granted patents·444 citations·filing 1990–1997
93Inventor score
Top patents by PatentIndex Score
11 records- 0178US5856927AMethod for automatically routing circuits of very large scale integration (VLSI)VLSI TECHNOLOGY INC·Filed 1995·Granted Jan 5, 1999·112 cites·20 claims
- 0278US5313079AGate array bases with flexible routingVLSI TECHNOLOGY INC·Filed 1992·Granted May 17, 1994·50 cites·5 claims
- 0375US5974245AMethod and apparatus for making integrated circuits by inserting buffers into a netlistVSLI TECHNOLOGY INC·Filed 1997·Granted Oct 26, 1999·69 cites·20 claims
- 0475US5638291AMethod and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skewVLSI TECHNOLOGY INC·Filed 1994·Granted Jun 10, 1997·63 cites·20 claims
- 0561US5521836AMethod for determining instance placements in circuit layoutsVLSI TECHNOLOGY INC·Filed 1994·Granted May 28, 1996·35 cites·17 claims
- 0659US5197015ASystem and method for setting capacitive constraints on synthesized logic circuitsVLSI TECHNOLOGY INC·Filed 1990·Granted Mar 23, 1993·35 cites·8 claims
- 0755US5367469APredictive capacitance layout method for integrated circuitsVLSI TECHNOLOGY INC·Filed 1990·Granted Nov 22, 1994·24 cites·15 claims
- 0854US5399517AMethod of routing three layer metal gate arrays using a channel routerVLSI TECHNOLOGY INC·Filed 1992·Granted Mar 21, 1995·17 cites·8 claims
- 0942USRE35671EPredictive capacitance layout method for integrated circuitsVLSI TECHNOLOGY INC·Filed 1996·Granted Nov 25, 1997·12 cites·15 claims
- 1042US5193092AIntegrated parity-based testing for integrated circuitsVLSI TECHNOLOGY INC·Filed 1990·Granted Mar 9, 1993·17 cites·8 claims
- 1139US5295088AMethod for predicting capacitance of connection nets on an integrated circuitVLSI TECHNOLOGY INC·Filed 1993·Granted Mar 15, 1994·10 cites·11 claims
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