Inventor · disambiguated record
Masaya Kibune
Also filed as: KIBUNE MASAYA
20 granted patents·7 pending applications·157 citations·filing 2002–2025
94Inventor score
Top patents by PatentIndex Score
27 records- 0190US6812777B2Output circuit device for clock signal distribution in high-speed signal transmissionFUJITSU LTD·Filed 2002·Granted Nov 2, 2004·44 cites·24 claims
- 0286US6963237B2Output circuit device for clock signal distribution in high-speed signal transmissionFUJITSU LTD·Filed 2004·Granted Nov 8, 2005·30 cites·6 claims
- 0383US8588359B2Reception circuit, reception method, and signal transfer systemKIBUNE MASAYA·Filed 2010·Granted Nov 19, 2013·10 cites·20 claims
- 0480US8797076B2Duty ratio correction circuit, double-edged device, and method of correcting duty ratioFUJITSU LTD·Filed 2013·Granted Aug 5, 2014·5 cites·10 claims
- 0580US7598780B2Clock bufferFUJITSU LTD·Filed 2007·Granted Oct 6, 2009·11 cites·13 claims
- 0680US7508892B2Receiver circuit comprising equalizerFUJITSU LTD·Filed 2005·Granted Mar 24, 2009·9 cites·13 claims
- 0778US8319542B2Integrated circuit including bypass signal pathTAMURA HIROTAKA·Filed 2006·Granted Nov 27, 2012·10 cites·10 claims
- 0878US7973691B2Data recovery circuit, data recovery method and data receiving apparatusFUJITSU LTD·Filed 2009·Granted Jul 5, 2011·7 cites·15 claims
- 0976US9509327B2A/D converter and A/D converter calibrating methodFUJITSU LTD·Filed 2016·Granted Nov 29, 2016·4 cites·14 claims
- 1073US8299948B2Receiving circuit and sampling clock control methodSHIBASAKI TAKAYUKI·Filed 2011·Granted Oct 30, 2012·4 cites·16 claims
- 1171US11138505B2Quantization of neural network parametersFUJITSU LTD·Filed 2017·Granted Oct 5, 2021·2 cites·14 claims
- 1267US8031091B2Reception circuit, method of creating AD converter conversion table of reception circuit, and signal transfer systemFUJITSU LTD·Filed 2010·Granted Oct 4, 2011·2 cites·13 claims
- 1366US8238504B2Clock generation circuit and systemTOMITA YASUMOTO·Filed 2009·Granted Aug 7, 2012·6 cites·15 claims
- 1464US7859300B2Input and output circuit apparatusFUJITSU LTD·Filed 2009·Granted Dec 28, 2010·4 cites·10 claims
- 1562US9118451B2Receiver circuit and receiving methodFUJITSU LTD·Filed 2014·Granted Aug 25, 2015·1 cites·14 claims
- 1662US7936296B2AD converter, data receiver and data reception methodFUJITSU LTD·Filed 2009·Granted May 3, 2011·4 cites·13 claims
- 1761US8320503B2ReceiverTAMURA HIROTAKA·Filed 2010·Granted Nov 27, 2012·1 cites·9 claims
- 1860US2025328804A1Computer-readable recording medium storing information processing program, information processing method, and information processing deviceFUJITSU LTD·Filed 2025·Application pending·0 cites
- 1955US7283601B2Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitryFUJITSU LTD·Filed 2002·Granted Oct 16, 2007·3 cites·25 claims
- 2050US2010011265A1Integrated circuit chip and circuit networkFUJITSU LTD·Filed 2009·Application pending·0 cites
- 2149US2013314142A1Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmissionFUJITSU LTD·Filed 2013·Application pending·0 cites
- 2246US8798568B2Signal transmission method, transmission circuit and apparatusKIBUNE MASAYA·Filed 2009·Granted Aug 5, 2014·0 cites·20 claims
- 2346US2009179674A1Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmissionFUJITSU LTD·Filed 2009·Application pending·0 cites
- 2445US2011221506A1Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmissionFUJITSU LTD·Filed 2011·Application pending·0 cites
- 2540US8634454B2Receiver circuit, method of adjusting offset, and transmission/reception systemKIBUNE MASAYA·Filed 2010·Granted Jan 21, 2014·0 cites·16 claims
- 2639US2019197395A1Model ensemble generationFUJITSU LTD·Filed 2017·Application pending·0 cites
- 2736US2017359153A1Measuring delay line linearity characteristicsFUJITSU LTD·Filed 2016·Application pending·0 cites
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