Inventor · disambiguated record
Charles Roberts Moore
Also filed as: MOORE CHARLES R · MOORE CHARLES ROBERTS
22 granted patents·3 pending applications·1,078 citations·filing 1992–2011
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0195US6728866B1Partitioned issue queue and allocation strategyIBM·Filed 2000·Granted Apr 27, 2004·122 cites·17 claims
- 0292US5724565AMethod and system for processing first and second sets of instructions by first and second types of processing systemsIBM·Filed 1995·Granted Mar 3, 1998·200 cites·16 claims
- 0389US6609190B1Microprocessor with primary and secondary issue queueIBM·Filed 2000·Granted Aug 19, 2003·58 cites·19 claims
- 0488US6725354B1Shared execution unit in a dual core processorIBM·Filed 2000·Granted Apr 20, 2004·50 cites·18 claims
- 0586US6766442B1Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register valueIBM·Filed 2000·Granted Jul 20, 2004·46 cites·3 claims
- 0686US6662294B1Converting short branches to predicated instructionsIBM·Filed 2000·Granted Dec 9, 2003·47 cites·24 claims
- 0785US5611058ASystem and method for transferring information between multiple busesIBM·Filed 1996·Granted Mar 11, 1997·126 cites·23 claims
- 0884US5437017AMethod and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing systemIBM·Filed 1992·Granted Jul 25, 1995·109 cites·14 claims
- 0981US6748519B1Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the registerIBM·Filed 2000·Granted Jun 8, 2004·33 cites·23 claims
- 1080US6678820B1Processor and method for separately predicting conditional branches dependent on lock acquisitionIBM·Filed 2000·Granted Jan 13, 2004·29 cites·14 claims
- 1177US6625746B1Microprocessor instruction buffer redundancy schemeIBM·Filed 2000·Granted Sep 23, 2003·23 cites·39 claims
- 1270US6938148B2Managing load and store operations using a storage management unit with data flow architectureIBM·Filed 2000·Granted Aug 30, 2005·15 cites·55 claims
- 1366US6658558B1Branch prediction circuit selector with instruction context related condition type determiningIBM·Filed 2000·Granted Dec 2, 2003·12 cites·22 claims
- 1465US6654869B1Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handlingIBM·Filed 1999·Granted Nov 25, 2003·43 cites·17 claims
- 1565US5706464AMethod and system for achieving atomic memory references in a multilevel cache data processing systemIBM·Filed 1996·Granted Jan 6, 1998·48 cites·6 claims
- 1662US5442766AMethod and system for distributed instruction address translation in a multiscalar data processing systemIBM·Filed 1992·Granted Aug 15, 1995·40 cites·10 claims
- 1758US5500950AData processor with speculative data transfer and address-free retryMOTOROLA INC·Filed 1993·Granted Mar 19, 1996·31 cites·13 claims
- 1847US5848283AMethod and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronizationIBM·Filed 1993·Granted Dec 8, 1998·23 cites·12 claims
- 1941US6658555B1Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipelineIBM·Filed 1999·Granted Dec 2, 2003·12 cites·17 claims
- 2041US2002156999A1Mixed-mode hardware multithreadingIBM·Filed 2001·Application pending·0 cites
- 2141US2002073301A1Hardware for use with compiler generated branch informationIBM·Filed 2000·Application pending·0 cites
- 2240US2012229481A1Accessibility of graphics processing compute resourcesMCCRARY REX·Filed 2011·Application pending·0 cites
- 2333US5793986AMethod and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing systemIBM·Filed 1995·Granted Aug 11, 1998·5 cites·14 claims
- 2431US5692218ASystem for transferring data between input/output devices having separate address spaces in accordance with initializing information in address packagesIBM·Filed 1996·Granted Nov 25, 1997·2 cites·20 claims
- 2531US5603057ASystem for initiating data transfer between input/output devices having separate address spaces in accordance with initializing information in two address packagesIBM·Filed 1995·Granted Feb 11, 1997·4 cites·20 claims
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