Inventor · disambiguated record
Michael B. Spear
Also filed as: SPEAR MICHAEL B
17 granted patents·3 pending applications·176 citations·filing 2005–2022
92Inventor score
Top patents by PatentIndex Score
20 records- 0197US9474034B1Power reduction in a parallel data communications interface using clock resynchronizationIBM·Filed 2015·Granted Oct 18, 2016·18 cites·13 claims
- 0295US8898504B2Parallel data communications mechanism having reduced power continuously calibrated linesBAUMGARTNER STEVEN J·Filed 2011·Granted Nov 25, 2014·57 cites·20 claims
- 0393US8139430B2Power-on initialization and test for a cascade interconnect memory systemBUCHMANN PETER L·Filed 2008·Granted Mar 20, 2012·46 cites·19 claims
- 0490US8681839B2Calibration of multiple parallel data communications lines for high skew conditionsBULZACCHELLI JOHN F·Filed 2010·Granted Mar 25, 2014·16 cites·22 claims
- 0586US10698440B2Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interfaceIBM·Filed 2018·Granted Jun 30, 2020·6 cites·20 claims
- 0686US7412618B2Combined alignment scrambler function for elastic interfaceIBM·Filed 2005·Granted Aug 12, 2008·13 cites·1 claims
- 0782US8767531B2Dynamic fault detection and repair in a data communications mechanismFERRAIOLO FRANK D·Filed 2011·Granted Jul 1, 2014·10 cites·12 claims
- 0874US9092312B2System and method to inject a bit error on a bus laneIBM·Filed 2012·Granted Jul 28, 2015·3 cites·20 claims
- 0970US10608763B2Built-in self-test for receiver channelIBM·Filed 2018·Granted Mar 31, 2020·2 cites·20 claims
- 1068US10901936B2Staged power on/off sequence at the I/O phy level in an interchip interfaceIBM·Filed 2016·Granted Jan 26, 2021·1 cites·20 claims
- 1168US9715270B2Power reduction in a parallel data communications interface using clock resynchronizationIBM·Filed 2016·Granted Jul 25, 2017·1 cites·16 claims
- 1265US8001412B2Combined alignment scrambler function for elastic interfaceIBM·Filed 2008·Granted Aug 16, 2011·2 cites·8 claims
- 1364US11099601B2Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interfaceIBM·Filed 2019·Granted Aug 24, 2021·1 cites·20 claims
- 1457US11907074B2Low-latency deserializer having fine granularity and defective-lane compensationIBM·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 1555US11973630B1Calibrating a quadrature receive serial interfaceIBM·Filed 2022·Granted Apr 30, 2024·0 cites·20 claims
- 1653US10162773B1Double data rate (DDR) memory read latency reductionIBM·Filed 2017·Granted Dec 25, 2018·0 cites·20 claims
- 1751US2013188656A1Communicating Control Information for a Data Communications Link Via a Line Being CalibratedIBM·Filed 2013·Application pending·0 cites
- 1847US2009276559A1Arrangements for Operating In-Line Memory Module ConfigurationsIBM·Filed 2008·Application pending·0 cites
- 1944US10771068B2Reducing chip latency at a clock boundary by reference clock phase adjustmentIBM·Filed 2018·Granted Sep 8, 2020·0 cites·14 claims
- 2042US2012106539A1Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant LinesFERRAIOLO FRANK D·Filed 2010·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →