Inventor

SHAH UDAY

US133 patents

⚠️ This page may combine multiple inventors who share the name “SHAH UDAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAH UDAY

INTEL CORP

Unity beta ratio tri-gate transistor static random access memory (SRAM)

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Block contact architectures for nanoscale channel transistors

Tri-gate patterning using dual layer gate stack

Methods for patterning a semiconductor film

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Stacked multi-gate transistor design and method of fabrication

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Nonplanar transistors with metal gate electrodes

Method of forming a metal oxide dielectric

Block contact architectures for nanoscale channel transistors

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

U-gate transistors and methods of fabrication

Nonplanar device with thinned lower body portion and method of fabrication

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Forming high-k dielectric layers on smooth substrates

Method for making a semiconductor device that includes a metal gate electrode

Planarizing a semiconductor structure to form replacement metal gates

Nonplanar transistors with metal gate electrodes

Forming integrated circuits with replacement metal gate electrodes

Methods for inducing strain in non-planar transistor structures

Apparatus and method for selectively recessing spacers on multi-gate devices

Method for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device with a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for etching a thin metal layer

Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction

Selective etch process for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a metal gate electrode

Etching metal carbide films

Techniques for forming non-planar resistive memory cells

Hybrid phase field effect transistor

III-N material structure for gate-recessed transistors

DOYLE BRIAN S

Vertical transistor devices for embedded memory and logic technologies

Vertical nanowire transistor with axially engineered semiconductor and gate metallization

Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same

PILLARISETTY RAVI

Non-planar germanium quantum well devices

Non-planar germanium quantum well devices

SHAH UDAY

Nonplanar device with thinned lower body portion and method of fabrication

Nonplanar device with thinned lower body portion and method of fabrication

BRASK JUSTIN K

Semiconductor device structures and methods of forming semiconductor structures

RACHMADY WILLY

Multi-gate device having a T-shaped gate structure

KAVALIEROS JACK T

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

OGUZ KAAN

Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer