Inventor · disambiguated record
Joel S. Emer
Also filed as: EMER JOEL · EMER JOEL S · EMER JOEL SPRINGER
54 granted patents·7 pending applications·2,698 citations·filing 1993–2021
99Inventor score
Files withINTEL CORP16NVIDIA CORP11DIGITAL EQUIPMENT CORP7STEELY JR SIMON C7HEWLETT PACKARD DEVELOPMENT CO5
Top patents by PatentIndex Score
61 records- 0198US10891538B2Sparse convolutional neural network acceleratorNVIDIA CORP·Filed 2017·Granted Jan 12, 2021·331 cites·20 claims
- 0298US10860922B2Sparse convolutional neural network acceleratorNVIDIA CORP·Filed 2019·Granted Dec 8, 2020·301 cites·20 claims
- 0398US10528864B2Sparse convolutional neural network acceleratorNVIDIA CORP·Filed 2017·Granted Jan 7, 2020·306 cites·18 claims
- 0495US6493741B1Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unitCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Dec 10, 2002·211 cites·60 claims
- 0594US11847550B2Sparse convolutional neural network acceleratorNVIDIA CORP·Filed 2020·Granted Dec 19, 2023·3 cites·20 claims
- 0694US6675192B2Temporary halting of thread execution until monitoring of armed events to memory location identified in working registersHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·92 cites·5 claims
- 0794US6470443B1Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count informationCOMPAQ COMPUTER CORP·Filed 2000·Granted Oct 22, 2002·104 cites·8 claims
- 0893US7627735B2Implementing vector memory operationsINTEL CORP·Filed 2005·Granted Dec 1, 2009·45 cites·28 claims
- 0991US10331583B2Executing distributed memory operations using processing elements connected by distributed channelsINTEL CORP·Filed 2013·Granted Jun 25, 2019·26 cites·21 claims
- 1091US7243262B2Incremental checkpointing in a multi-threaded architectureINTEL CORP·Filed 2003·Granted Jul 10, 2007·67 cites·29 claims
- 1191US5758142ATrainable apparatus for predicting instruction outcomes in pipelined processorsDIGITAL EQUIPMENT CORP·Filed 1994·Granted May 26, 1998·176 cites·31 claims
- 1289US6073159AThread properties attribute vector based thread selection in multithreading processorCOMPAQ COMPUTER CORP·Filed 1996·Granted Jun 6, 2000·150 cites·71 claims
- 1388US7308607B2Periodic checkpointing in a redundantly multi-threaded architectureINTEL CORP·Filed 2003·Granted Dec 11, 2007·55 cites·40 claims
- 1486US7373548B2Hardware recovery in a multi-threaded architectureINTEL CORP·Filed 2003·Granted May 13, 2008·42 cites·27 claims
- 1583US7475321B2Detecting errors in directory entriesINTEL CORP·Filed 2004·Granted Jan 6, 2009·32 cites·13 claims
- 1680US10997496B2Sparse convolutional neural network acceleratorNVIDIA CORP·Filed 2017·Granted May 4, 2021·3 cites·20 claims
- 1780US9262327B2Signature based hit-predicting cacheSTEELY JR SIMON C·Filed 2012·Granted Feb 16, 2016·6 cites·26 claims
- 1880US9037804B2Efficient support of sparse data structure accessSTEELY JR SIMON C·Filed 2011·Granted May 19, 2015·5 cites·13 claims
- 1980US6108770AMethod and apparatus for predicting memory dependence using store setsDIGITAL EQUIPMENT CORP·Filed 1998·Granted Aug 22, 2000·93 cites·39 claims
- 2080US5285323AIntegrated circuit chip having primary and secondary random access memories for a hierarchical cacheDIGITAL EQUIPMENT CORP·Filed 1993·Granted Feb 8, 1994·96 cites·16 claims
- 2179US7747932B2Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy systemINTEL CORP·Filed 2005·Granted Jun 29, 2010·10 cites·17 claims
- 2278US5933860AMultiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predictedDIGITAL EQUIPMENT CORP·Filed 1997·Granted Aug 3, 1999·81 cites·21 claims
- 2376US7343602B2Software controlled pre-execution in a multithreaded processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Mar 11, 2008·25 cites·36 claims
- 2476US7003648B2Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPUHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Feb 21, 2006·24 cites·32 claims
- 2574US11270197B2Efficient neural network accelerator dataflowsNVIDIA CORP·Filed 2019·Granted Mar 8, 2022·2 cites·7 claims
- 2674US5421022AApparatus and method for speculatively executing instructions in a computer systemDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 30, 1995·67 cites·21 claims
- 2773US8707012B2Implementing vector memory operationsESPASA ROGER·Filed 2012·Granted Apr 22, 2014·3 cites·20 claims
- 2872US7558920B2Apparatus and method for partitioning a shared cache of a chip multi-processorINTEL CORP·Filed 2004·Granted Jul 7, 2009·24 cites·30 claims
- 2972US7543221B2Method and apparatus for reducing false error detection in a redundant multi-threaded systemINTEL CORP·Filed 2004·Granted Jun 2, 2009·14 cites·19 claims
- 3072US7404070B1Branch prediction combining static and dynamic prediction techniquesHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jul 22, 2008·18 cites·15 claims
- 3172US6081887ASystem for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instructionCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 27, 2000·62 cites·18 claims
- 3271US8769201B2Technique for controlling computing resourcesHASENPLAUGH WILLIAM·Filed 2008·Granted Jul 1, 2014·7 cites·28 claims
- 3370US10853276B2Executing distributed memory operations using processing elements connected by distributed channelsINTEL CORP·Filed 2019·Granted Dec 1, 2020·1 cites·24 claims
- 3470US9740617B2Hardware apparatuses and methods to control cache line coherenceINTEL CORP·Filed 2014·Granted Aug 22, 2017·2 cites·24 claims
- 3570US8316216B2Implementing vector memory operationsESPASA ROGER·Filed 2009·Granted Nov 20, 2012·4 cites·20 claims
- 3669US12387089B2Efficient neural network accelerator dataflowsNVIDIA CORP·Filed 2021·Granted Aug 12, 2025·0 cites·15 claims
- 3768US7353365B2Implementing check instructions in each thread within a redundant multithreading environmentsINTEL CORP·Filed 2004·Granted Apr 1, 2008·12 cites·27 claims
- 3866US9201792B2Short circuit of probes in a chainSTEELY JR SIMON C·Filed 2011·Granted Dec 1, 2015·2 cites·12 claims
- 3965US11966835B2Deep neural network accelerator with fine-grained parallelism discoveryNVIDIA CORP·Filed 2019·Granted Apr 23, 2024·1 cites·20 claims
- 4065US6154828AMethod and apparatus for employing a cycle bit parallel executing instructionsCOMPAQ COMPUTER CORP·Filed 1993·Granted Nov 28, 2000·46 cites·26 claims
- 4164US5428807AMethod and apparatus for propagating exception conditions of a computer systemDIGITAL EQUIPMENT CORP·Filed 1993·Granted Jun 27, 1995·45 cites·9 claims
- 4263US9418016B2Method and apparatus for optimizing the usage of cache memoriesSTEELY JR SIMON C·Filed 2010·Granted Aug 16, 2016·1 cites·26 claims
- 4363US9146871B2Retrieval of previously accessed data in a multi-core processorSTEELY JR SIMON C·Filed 2011·Granted Sep 29, 2015·1 cites·20 claims
- 4463US5420990AMechanism for enforcing the correct order of instruction executionDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 30, 1995·43 cites·3 claims
- 4562US7444497B2Managing external memory updates for fault detection in redundant multithreading systems using speculative memory supportINTEL CORP·Filed 2003·Granted Oct 28, 2008·8 cites·17 claims
- 4659US7386756B2Reducing false error detection in a microprocessor by tracking instructions neutral to errorsINTEL CORP·Filed 2004·Granted Jun 10, 2008·6 cites·30 claims
- 4757US7555703B2Method and apparatus for reducing false error detection in a microprocessorINTEL CORP·Filed 2004·Granted Jun 30, 2009·4 cites·40 claims
- 4856US8769209B2Method and apparatus for achieving non-inclusive cache performance with inclusive cachesJALEEL AAMER·Filed 2010·Granted Jul 1, 2014·1 cites·19 claims
- 4951US11769040B2Scalable multi-die deep learning systemNVIDIA CORP·Filed 2019·Granted Sep 26, 2023·0 cites·19 claims
- 5051US2022083500A1Flexible accelerator for a tensor workloadNVIDIA CORP·Filed 2021·Application pending·0 cites
Showing the top 50 of 61 patent records by PatentIndex Score.
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