Inventor · disambiguated record
Philippe Gayet
Also filed as: GAYET PHILIPPE
10 granted patents·117 citations·filing 1991–2003
89Inventor score
Files withST MICROELECTRONICS SA5SGS THOMSON MICROELECTRONICS3FRANCE TELECOM CNET1KONINKL PHILIPS ELECTRONICS NV1
Top patents by PatentIndex Score
10 records- 0184US6451669B2Method of forming insulated metal interconnections in integrated circuitsST MICROELECTRONICS SA·Filed 2000·Granted Sep 17, 2002·36 cites·7 claims
- 0258US6239025B1High aspect ratio contact structure for use in integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1997·Granted May 29, 2001·32 cites·15 claims
- 0353US6762497B2Integrated circuit with stop layer and associated fabrication processST MICROELECTRONICS SA·Filed 2001·Granted Jul 13, 2004·5 cites·10 claims
- 0447US5736451AMethod of forming planar isolation in integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Apr 7, 1998·13 cites·11 claims
- 0546US6392299B1Integrated circuit and associated fabrication processST MICROELECTRONICS SA·Filed 1999·Granted May 21, 2002·14 cites·18 claims
- 0644US7064053B2Process for fabricating an electrical circuit comprising a polishing stepKONINKL PHILIPS ELECTRONICS NV·Filed 2003·Granted Jun 20, 2006·2 cites·32 claims
- 0740US6580130B1Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistorsST MICROELECTRONICS SA·Filed 1999·Granted Jun 17, 2003·9 cites·12 claims
- 0835US6355552B1Integrated circuit with stop layer and associated fabrication processST MICROELECTRONICS SA·Filed 1999·Granted Mar 12, 2002·5 cites·7 claims
- 0928US6525393B1Semiconductor substrate having an isolation regionSGS THOMSON MICROELECTRONICS·Filed 1998·Granted Feb 25, 2003·0 cites·4 claims
- 1024US5186786AMethod for determining the complete elimination of a thin layer on a non planar substrateFRANCE TELECOM CNET·Filed 1991·Granted Feb 16, 1993·1 cites·6 claims
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