Inventor · disambiguated record
Nadia Galbiati
Also filed as: GALBIATI NADIA
15 granted patents·156 citations·filing 1999–2001
93Inventor score
Files withST MICROELECTRONICS SRL15
Top patents by PatentIndex Score
15 records- 0175US6624015B2Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted Sep 23, 2003·17 cites·12 claims
- 0274US6281077B1Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Aug 28, 2001·27 cites·13 claims
- 0370US6521957B2Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 2000·Granted Feb 18, 2003·10 cites·7 claims
- 0470US6420769B2Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted Jul 16, 2002·13 cites·12 claims
- 0562US6251728B1Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Jun 26, 2001·17 cites·12 claims
- 0660US6573130B1Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistorsST MICROELECTRONICS SRL·Filed 1999·Granted Jun 3, 2003·17 cites·11 claims
- 0760US6351008B1Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Feb 26, 2002·17 cites·8 claims
- 0855US6274411B1Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masksST MICROELECTRONICS SRL·Filed 1999·Granted Aug 14, 2001·14 cites·19 claims
- 0945US6396101B2Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted May 28, 2002·2 cites·7 claims
- 1044US6414349B1High efficiency memory deviceST MICROELECTRONICS SRL·Filed 2000·Granted Jul 2, 2002·2 cites·18 claims
- 1143US6576517B1Method for obtaining a multi-level ROM in an EEPROM process flowST MICROELECTRONICS SRL·Filed 1999·Granted Jun 10, 2003·8 cites·10 claims
- 1239US6177313B1Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 1999·Granted Jan 23, 2001·4 cites·9 claims
- 1337US6300181B1Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistorsST MICROELECTRONICS SRL·Filed 1999·Granted Oct 9, 2001·5 cites·15 claims
- 1434US6284607B1Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicideST MICROELECTRONICS SRL·Filed 1999·Granted Sep 4, 2001·3 cites·13 claims
- 1530US6444526B1Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cellsST MICROELECTRONICS SRL·Filed 1999·Granted Sep 3, 2002·0 cites·8 claims
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