Inventor · disambiguated record
Stephen J. Ciavaglia
Also filed as: CIAVAGLIA STEPHEN · CIAVAGLIA STEPHEN J
14 granted patents·759 citations·filing 1988–2001
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0188US5615350AApparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatching, issuing and executing multiple instructions in a single processor cycleIBM·Filed 1995·Granted Mar 25, 1997·149 cites·4 claims
- 0286US5175829AMethod and apparatus for bus lock during atomic computer operationsHEWLETT PACKARD CO·Filed 1988·Granted Dec 29, 1992·107 cites·9 claims
- 0384US7222268B2System resource availability managerENTERASYS NETWORKS INC·Filed 2001·Granted May 22, 2007·42 cites·91 claims
- 0483US5666506AApparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycleIBM·Filed 1995·Granted Sep 9, 1997·106 cites·1 claims
- 0580US5884061AApparatus to perform source operand dependency analysis perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single processor cycleIBM·Filed 1995·Granted Mar 16, 1999·97 cites·4 claims
- 0678US5625789AApparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycleIBM·Filed 1994·Granted Apr 29, 1997·77 cites·5 claims
- 0767US5051885AData processing system for concurrent dispatch of instructions to multiple functional unitsHEWLETT PACKARD CO·Filed 1988·Granted Sep 24, 1991·40 cites·10 claims
- 0866US5625787ASuperscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cacheIBM·Filed 1995·Granted Apr 29, 1997·43 cites·20 claims
- 0963US5193157APiplined system includes a selector for loading condition code either from first or second condition code registers to program counterHEWLETT PACKARD CO·Filed 1991·Granted Mar 9, 1993·45 cites·3 claims
- 1055US5644744ASuperscaler instruction pipeline having boundary identification logic for variable length instructionsIBM·Filed 1995·Granted Jul 1, 1997·25 cites·18 claims
- 1135US5640526ASuperscaler instruction pipeline having boundary indentification logic for variable length instructionsIBM·Filed 1994·Granted Jun 17, 1997·6 cites·16 claims
- 1235US5045992AApparatus for executing instruction regardless of data types and thereafter selectively branching to other instruction upon determining of incompatible data typeHEWLETT PACKARD CO·Filed 1988·Granted Sep 3, 1991·6 cites·12 claims
- 1332US6292826B1Shadow arrays for distributed memory multiprocessor architectureALCATEL INTERNETWORKING INC·Filed 1998·Granted Sep 18, 2001·7 cites·20 claims
- 1431US6397306B2Per memory atomic access for distributed memory multiprocessor architectureALCATEL INTERNETWORKING INC·Filed 1998·Granted May 28, 2002·9 cites·23 claims
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