Inventor · disambiguated record
Jenn Ming Huang
Also filed as: HUANG JENN M · HUANG JENN MING
68 granted patents·1 pending application·2,683 citations·filing 1995–2004
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG68
Top patents by PatentIndex Score
69 records- 0196US6037222AMethod for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technologyTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 14, 2000·148 cites·15 claims
- 0294US6033963AMethod of forming a metal gate for CMOS devices using a replacement gate processTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Mar 7, 2000·225 cites·18 claims
- 0393US6353269B1Method for making cost-effective embedded DRAM structures compatible with logic circuit processingTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Mar 5, 2002·56 cites·5 claims
- 0493US6255160B1Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cellsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 3, 2001·80 cites·26 claims
- 0592US6187624B1Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) deviceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 13, 2001·94 cites·26 claims
- 0692US6100118AFabrication of metal fuse design for redundancy technology having a guard ringTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 8, 2000·116 cites·10 claims
- 0791US6096595AIntegration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devicesTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 1, 2000·101 cites·23 claims
- 0891US6074908AProcess for making merged integrated circuits having salicide FETS and embedded DRAM circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 13, 2000·84 cites·20 claims
- 0991US6042999ARobust dual damascene processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 28, 2000·120 cites·41 claims
- 1090US6251726B1Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillarTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jun 26, 2001·54 cites·21 claims
- 1190US6117725AMethod for making cost-effective embedded DRAM structures compatible with logic circuit processingTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 12, 2000·89 cites·16 claims
- 1288US5918120AMethod for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit linesTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jun 29, 1999·85 cites·29 claims
- 1387US6198173B1SRAM with improved Beta ratioTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 6, 2001·50 cites·7 claims
- 1487US6157064AMethod and a deep sub-micron field effect transistor structure for suppressing short channel effectsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Dec 5, 2000·71 cites·3 claims
- 1585US6436763B1Process for making embedded DRAM circuits having capacitor under bit-line (CUB)TAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·39 cites·20 claims
- 1685US5998252AMethod of salicide and sac (self-aligned contact) integrationTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Dec 7, 1999·53 cites·15 claims
- 1785US5863820AIntegration of sac and salicide processes on a chip having embedded memoryTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 26, 1999·81 cites·15 claims
- 1883US6127260AMethod of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devicesTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 3, 2000·70 cites·21 claims
- 1983US5525552AMethod for fabricating a MOSFET device with a buried contactTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted Jun 11, 1996·63 cites·29 claims
- 2081US5989966AMethod and a deep sub-micron field effect transistor structure for suppressing short channel effectsTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Nov 23, 1999·53 cites·20 claims
- 2180US6617631B2Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) deviceTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 9, 2003·23 cites·6 claims
- 2279US6117723ASalicide integration process for embedded DRAM devicesTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 12, 2000·46 cites·22 claims
- 2377US6100116AMethod to form a protected metal fuseTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 8, 2000·51 cites·9 claims
- 2477US6015730AIntegration of SAC and salicide processes by combining hard mask and poly definitionTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 18, 2000·54 cites·15 claims
- 2576US6579784B1Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacersTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 17, 2003·38 cites·15 claims
- 2676US6235593B1Self aligned contact using spacers on the ILD layer sidewallsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 22, 2001·50 cites·10 claims
- 2775US6825078B1Single poly-Si process for DRAM by deep N well (NW) plateTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Nov 30, 2004·13 cites·16 claims
- 2874US5607881AMethod of reducing buried contact resistance in SRAMTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted Mar 4, 1997·36 cites·30 claims
- 2973US6004843AProcess for integrating a MOS logic device and a MOS memory device on a single semiconductor chipTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 21, 1999·46 cites·28 claims
- 3073US5821141AMethod for forming a cylindrical capacitor in DRAM having pin plug profileTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Oct 13, 1998·31 cites·25 claims
- 3172US6406987B1Method for making borderless contacts to active device regions and overlaying shallow trench isolation regionsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jun 18, 2002·43 cites·30 claims
- 3272US6274471B1Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask techniqueTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 14, 2001·41 cites·20 claims
- 3372US6103622ASilicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET deviceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 15, 2000·25 cites·21 claims
- 3470US7030440B2Single poly-si process for DRAM by deep N-well (NW) plateTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 18, 2006·10 cites·13 claims
- 3569US6025279AMethod of reducing nitride and oxide peeling after planarization using an annealTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Feb 15, 2000·34 cites·19 claims
- 3668US6093640AOverlay measurement improvement between damascene metal interconnectionsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 25, 2000·36 cites·18 claims
- 3768US5899722AMethod of forming dual spacer for self aligned contact integrationTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 4, 1999·35 cites·7 claims
- 3868US5872030AMethod of improving beta ratio in SRAM and device manufactured therebyTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Feb 16, 1999·21 cites·11 claims
- 3964US6351016B1Technology for high performance buried contact and tungsten polycide gate integrationTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 26, 2002·19 cites·10 claims
- 4063US5924011ASilicide process for mixed mode productTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jul 13, 1999·17 cites·21 claims
- 4161US5918119AProcess for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 29, 1999·20 cites·22 claims
- 4260US6037199ASOI device for DRAM cells beyond gigabit generation and method for making the sameTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Mar 14, 2000·17 cites·21 claims
- 4360US5854119ARobust method of forming a cylinder capacitor for DRAM circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 29, 1998·24 cites·20 claims
- 4459US6001721ASilicide and salicide on the same chipTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 14, 1999·19 cites·20 claims
- 4557US6137179AMethod for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit linesTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 24, 2000·18 cites·5 claims
- 4657US6103621ASilicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET deviceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 15, 2000·13 cites·21 claims
- 4755US5494843AMethod for forming MOSFET devicesTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted Feb 27, 1996·20 cites·30 claims
- 4852US6015735AMethod for forming a multi-anchor DRAM capacitor and capacitor formedTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 18, 2000·13 cites·20 claims
- 4951US7119017B2Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratiosTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 10, 2006·1 cites·28 claims
- 5050US7037776B2Single polysilicon process for DRAMTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted May 2, 2006·4 cites·45 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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