Inventor · disambiguated record
Paul A. Merolla
Also filed as: MEROLLA PAUL A
74 granted patents·1 pending application·563 citations·filing 2010–2021
99Inventor score
Top patents by PatentIndex Score
75 records- 0196US9466022B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2015·Granted Oct 11, 2016·21 cites·20 claims
- 0296US8812414B2Low-power event-driven neural computing architecture in neural networksARTHUR JOHN V·Filed 2011·Granted Aug 19, 2014·74 cites·25 claims
- 0395US9244124B2Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputsIBM·Filed 2014·Granted Jan 26, 2016·12 cites·20 claims
- 0495US8909576B2Neuromorphic event-driven neural computing architecture in a scalable neural networkAKOPYAN FILIPP·Filed 2011·Granted Dec 9, 2014·56 cites·12 claims
- 0594US8990130B2Consolidating multiple neurosynaptic cores into one memoryIBM·Filed 2012·Granted Mar 24, 2015·42 cites·25 claims
- 0693US9971965B2Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithmIBM·Filed 2015·Granted May 15, 2018·14 cites·20 claims
- 0793US9818058B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptationIBM·Filed 2016·Granted Nov 14, 2017·13 cites·15 claims
- 0893US9160617B2Faulty core recovery mechanisms for a three-dimensional network on a processor arrayIBM·Filed 2012·Granted Oct 13, 2015·16 cites·25 claims
- 0991US9992057B2Yield tolerance in a neurosynaptic systemIBM·Filed 2014·Granted Jun 5, 2018·12 cites·20 claims
- 1090US9159020B2Multiplexing physical neurons to optimize power and areaALCAREZ-ICAZA RIVERA RODRIGO·Filed 2012·Granted Oct 13, 2015·44 cites·23 claims
- 1188US11630516B1Brain-machine interface (BMI) with user interface (UI) aware controllerNEURALINK CORP·Filed 2021·Granted Apr 18, 2023·4 cites·12 claims
- 1288US9704094B2Mapping of algorithms to neurosynaptic hardwareIBM·Filed 2015·Granted Jul 11, 2017·10 cites·20 claims
- 1388US9373073B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptationIBM·Filed 2012·Granted Jun 21, 2016·20 cites·31 claims
- 1487US10204301B2Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrateIBM·Filed 2015·Granted Feb 12, 2019·8 cites·20 claims
- 1587US9984324B2Dual deterministic and stochastic neurosynaptic core circuitIBM·Filed 2016·Granted May 29, 2018·6 cites·14 claims
- 1687US9269044B2Neuromorphic event-driven neural computing architecture in a scalable neural networkAKOPYAN FILIPP·Filed 2012·Granted Feb 23, 2016·16 cites·20 claims
- 1787US8473439B2Integrate and fire electronic neuronsARTHUR JOHN V·Filed 2010·Granted Jun 25, 2013·20 cites·25 claims
- 1886US10454759B2Yield tolerance in a neurosynaptic systemIBM·Filed 2018·Granted Oct 22, 2019·3 cites·18 claims
- 1986US9940302B2Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor arrayIBM·Filed 2016·Granted Apr 10, 2018·4 cites·20 claims
- 2086US8990616B2Final faulty core recovery mechanisms for a two-dimensional network on a processor arrayIBM·Filed 2012·Granted Mar 24, 2015·9 cites·25 claims
- 2185US9588937B2Array of processor core circuits with reversible tiersIBM·Filed 2013·Granted Mar 7, 2017·7 cites·20 claims
- 2285US9053429B2Mapping neural dynamics of a neural model on to a coarsely grained look-up tableIBM·Filed 2012·Granted Jun 9, 2015·12 cites·22 claims
- 2384US9852006B2Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuitsIBM·Filed 2014·Granted Dec 26, 2017·15 cites·20 claims
- 2484US9218564B2Providing transposable access to a synapse array using a recursive array layoutARTHUR JOHN V·Filed 2012·Granted Dec 22, 2015·12 cites·20 claims
- 2584US9087301B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2012·Granted Jul 21, 2015·11 cites·27 claims
- 2683US9239984B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural networkIBM·Filed 2012·Granted Jan 19, 2016·11 cites·20 claims
- 2782US10452540B2Memory-mapped interface for message passing computing systemsIBM·Filed 2017·Granted Oct 22, 2019·4 cites·27 claims
- 2881US10282658B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2016·Granted May 7, 2019·3 cites·15 claims
- 2981US9189729B2Scalable neural hardware for the noisy-OR model of Bayesian networksARTHUR JOHN V·Filed 2012·Granted Nov 17, 2015·10 cites·20 claims
- 3081US8918351B2Providing transposable access to a synapse array using column aggregationARTHUR JOHN V·Filed 2012·Granted Dec 23, 2014·6 cites·9 claims
- 3180US9563841B2Globally asynchronous and locally synchronous (GALS) neuromorphic networkALVAREZ-ICAZA RIVERA RODRIGO·Filed 2012·Granted Feb 7, 2017·12 cites·20 claims
- 3279US10331998B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural networkIBM·Filed 2015·Granted Jun 25, 2019·3 cites·15 claims
- 3379US9747545B2Self-timed, event-driven neurosynaptic core controllerIBM·Filed 2014·Granted Aug 29, 2017·9 cites·18 claims
- 3477US10504021B2Neuromorphic event-driven neural computing architecture in a scalable neural networkIBM·Filed 2016·Granted Dec 10, 2019·2 cites·20 claims
- 3577US9924490B2Scaling multi-core neurosynaptic networks across chip boundariesIBM·Filed 2013·Granted Mar 20, 2018·7 cites·20 claims
- 3676US10785745B2Scaling multi-core neurosynaptic networks across chip boundariesIBM·Filed 2017·Granted Sep 22, 2020·2 cites·18 claims
- 3775US9558443B2Dual deterministic and stochastic neurosynaptic core circuitIBM·Filed 2013·Granted Jan 31, 2017·6 cites·20 claims
- 3875US9424284B2Mapping neural dynamics of a neural model on to a coarsely grained look-up tableIBM·Filed 2015·Granted Aug 23, 2016·2 cites·17 claims
- 3973US10713561B2Multiplexing physical neurons to optimize power and areaIBM·Filed 2015·Granted Jul 14, 2020·2 cites·18 claims
- 4072US10410109B2Peripheral device interconnections for neurosynaptic systemsIBM·Filed 2014·Granted Sep 10, 2019·5 cites·20 claims
- 4171US10824579B2Network-on-chip for neurological dataNEURALINK CORP·Filed 2019·Granted Nov 3, 2020·1 cites·17 claims
- 4270US11663151B2Network-on-chip for neurological dataNEURALINK CORP·Filed 2021·Granted May 30, 2023·0 cites·19 claims
- 4370US9886662B2Converting spike event data to digital numeric dataIBM·Filed 2014·Granted Feb 6, 2018·4 cites·20 claims
- 4469US10984312B2Mapping graphs onto core-based neuromorphic architecturesIBM·Filed 2017·Granted Apr 20, 2021·1 cites·8 claims
- 4568US10832125B2Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithmIBM·Filed 2018·Granted Nov 10, 2020·1 cites·17 claims
- 4668US10769519B2Converting digital numeric data to spike event dataIBM·Filed 2017·Granted Sep 8, 2020·1 cites·20 claims
- 4767US9852370B2Mapping graphs onto core-based neuromorphic architecturesIBM·Filed 2014·Granted Dec 26, 2017·3 cites·15 claims
- 4866US10102474B2Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural networkIBM·Filed 2014·Granted Oct 16, 2018·3 cites·20 claims
- 4965US11216400B2Network-on-chip for neurological dataNEURALINK CORP·Filed 2020·Granted Jan 4, 2022·0 cites·17 claims
- 5063US11580366B2Neuromorphic event-driven neural computing architecture in a scalable neural networkIBM·Filed 2019·Granted Feb 14, 2023·0 cites·10 claims
Showing the top 50 of 75 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →