Inventor · disambiguated record
Jayen Desai
Also filed as: DESAI JAYEN · DESAI JAYEN J
11 granted patents·1 pending application·62 citations·filing 2000–2022
88Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO6FRANCOM ERIN D2DESAI JAYEN J1HEWLETT PACKARD CO1INTEL CORP1
Top patents by PatentIndex Score
12 records- 0190US7610526B2On-chip circuitry for bus validationHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Oct 27, 2009·22 cites·39 claims
- 0277US7276952B2Clock signal generation using digital frequency synthesizerHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Oct 2, 2007·8 cites·9 claims
- 0376US9628092B2Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuningFRANCOM ERIN D·Filed 2015·Granted Apr 18, 2017·4 cites·15 claims
- 0475US7873132B2Clock recoveryHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jan 18, 2011·7 cites·25 claims
- 0574US9178502B2Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuningFRANCOM ERIN D·Filed 2013·Granted Nov 3, 2015·4 cites·9 claims
- 0670US9124257B2Digital clock placement engine apparatus and method with duty cycle correction and quadrature placementDESAI JAYEN J·Filed 2011·Granted Sep 1, 2015·5 cites·19 claims
- 0763US7498858B2Interpolator systems with linearity adjustments and related methodsHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Mar 3, 2009·9 cites·14 claims
- 0860US12500583B2Clock interpolation system for eye-centeringINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 0945US6459304B1Latching annihilation based logic gateHEWLETT PACKARD CO·Filed 2000·Granted Oct 1, 2002·3 cites·10 claims
- 1041US2003062921A1Bi-directional transmission line termination systemFiled 2001·Application pending·0 cites
- 1135US7391221B2On-die impedance calibrationHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jun 24, 2008·0 cites·6 claims
- 1235US6583650B2Latching annihilation based logic gateHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 24, 2003·0 cites·23 claims
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