Inventor · disambiguated record
Brian Flachs
Also filed as: FLACHS BRIAN · FLACHS BRIAN K · FLACHS BRIAN KING
50 granted patents·10 pending applications·356 citations·filing 1999–2017
98Inventor score
Top patents by PatentIndex Score
60 records- 0195US8520740B2Arithmetic decoding accelerationFLACHS BRIAN·Filed 2010·Granted Aug 27, 2013·56 cites·21 claims
- 0293US7447602B1System and method for sorting processors based on thermal design pointIBM·Filed 2007·Granted Nov 4, 2008·27 cites·20 claims
- 0392US8522225B2Rewriting branch instructions using branch stubsCHEN TONG·Filed 2010·Granted Aug 27, 2013·18 cites·20 claims
- 0492US8381006B2Reducing power requirements of a multiple core processorIBM·Filed 2010·Granted Feb 19, 2013·16 cites·20 claims
- 0591US10169013B2Arranging binary code based on call graph partitioningIBM·Filed 2017·Granted Jan 1, 2019·5 cites·21 claims
- 0687US7533238B2Method for limiting the size of a local storage of a processorIBM·Filed 2005·Granted May 12, 2009·17 cites·12 claims
- 0784US8782381B2Dynamically rewriting branch instructions in response to cache line evictionCHEN TONG·Filed 2012·Granted Jul 15, 2014·7 cites·19 claims
- 0884US8631225B2Dynamically rewriting branch instructions to directly target an instruction cache locationCHEN TONG·Filed 2010·Granted Jan 14, 2014·7 cites·15 claims
- 0983US8713548B2Rewriting branch instructions using branch stubsCHEN TONG·Filed 2012·Granted Apr 29, 2014·6 cites·13 claims
- 1081US8627051B2Dynamically rewriting branch instructions to directly target an instruction cache locationCHEN TONG·Filed 2012·Granted Jan 7, 2014·5 cites·10 claims
- 1181US8516230B2SPE software instruction cacheCHEN TONG·Filed 2009·Granted Aug 20, 2013·10 cites·19 claims
- 1280US7203608B1Impedane measurement of chip, package, and board power supply system using pseudo impulse responseIBM·Filed 2006·Granted Apr 10, 2007·10 cites·20 claims
- 1379US7486096B2Method and apparatus for testing to determine minimum operating voltages in electronic devicesIBM·Filed 2006·Granted Feb 3, 2009·9 cites·20 claims
- 1477US9459851B2Arranging binary code based on call graph partitioningCHEN TONG·Filed 2010·Granted Oct 4, 2016·3 cites·14 claims
- 1575US9916144B2Arranging binary code based on call graph partitioningIBM·Filed 2016·Granted Mar 13, 2018·1 cites·19 claims
- 1675US8627043B2Data parallel function call for determining if called routine is data parallelEICHENBERGER ALEXANDRE E·Filed 2012·Granted Jan 7, 2014·3 cites·9 claims
- 1775US7617338B2Memory with combined line and word accessIBM·Filed 2005·Granted Nov 10, 2009·7 cites·20 claims
- 1874US7610531B2Modifying a test pattern to control power supply noiseIBM·Filed 2006·Granted Oct 27, 2009·7 cites·21 claims
- 1974US6598153B1Processor and method that accelerate evaluation of pairs of condition-setting and branch instructionsIBM·Filed 1999·Granted Jul 22, 2003·64 cites·17 claims
- 2073US8726252B2Management of conditional branches within a data parallel systemEICHENBERGER ALEXANDRE E·Filed 2011·Granted May 13, 2014·4 cites·6 claims
- 2172US9424173B2Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memoryGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 23, 2016·3 cites·21 claims
- 2272US6629235B1Condition code register architecture for supporting multiple execution unitsIBM·Filed 2000·Granted Sep 30, 2003·17 cites·12 claims
- 2368US9600253B2Arranging binary code based on call graph partitioningCHEN TONG·Filed 2012·Granted Mar 21, 2017·1 cites·7 claims
- 2468US8627042B2Data parallel function call for determining if called routine is data parallelEICHENBERGER ALEXANDRE E·Filed 2009·Granted Jan 7, 2014·3 cites·16 claims
- 2567US8359435B2Optimization of software instruction cache by line re-orderingIBM·Filed 2009·Granted Jan 22, 2013·4 cites·21 claims
- 2666US8683185B2Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second setFLACHS BRIAN·Filed 2010·Granted Mar 25, 2014·2 cites·12 claims
- 2766US7917347B2Generating a worst case current waveform for testing of integrated circuit devicesIBM·Filed 2007·Granted Mar 29, 2011·3 cites·20 claims
- 2866US6600959B1Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arraysIBM·Filed 2000·Granted Jul 29, 2003·12 cites·20 claims
- 2965US7689865B2Middlesoft commanderIBM·Filed 2006·Granted Mar 30, 2010·4 cites·17 claims
- 3065US7197655B2Lowered PU power usage method and apparatusIBM·Filed 2003·Granted Mar 27, 2007·11 cites·16 claims
- 3164US10345882B2Dynamic power meter with improved accuracy and single cycle resolutionMEDIATEK INC·Filed 2015·Granted Jul 9, 2019·1 cites·18 claims
- 3261US10324694B2Arranging binary code based on call graph partitioningIBM·Filed 2017·Granted Jun 18, 2019·0 cites·20 claims
- 3360US8572359B2Runtime extraction of data parallelismEICHENBERGER ALEXANDRE E·Filed 2009·Granted Oct 29, 2013·1 cites·18 claims
- 3460US7870309B2Multithreaded programmable direct memory access engineIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 3559US8595467B2Floating point collect and operateFLACHS BRIAN K·Filed 2009·Granted Nov 26, 2013·2 cites·12 claims
- 3659US7870308B2Programmable direct memory access engineIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 3755US9696995B2Parallel execution unit that extracts data parallelism at runtimeEICHENBERGER ALEXANDRE E·Filed 2009·Granted Jul 4, 2017·0 cites·20 claims
- 3854US9547597B2Selection of post-request action based on combined response and input from the request sourceIBM·Filed 2013·Granted Jan 17, 2017·0 cites·8 claims
- 3953US9606922B2Selection of post-request action based on combined response and input from the request sourceIBM·Filed 2013·Granted Mar 28, 2017·0 cites·19 claims
- 4053US7730279B2System for limiting the size of a local storage of a processorIBM·Filed 2009·Granted Jun 1, 2010·0 cites·20 claims
- 4152US8145804B2Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processorFLACHS BRIAN KING·Filed 2009·Granted Mar 27, 2012·1 cites·19 claims
- 4251US8918553B2Multithreaded programmable direct memory access engineFLACHS BRIAN K·Filed 2012·Granted Dec 23, 2014·0 cites·17 claims
- 4350US9696996B2Parallel execution unit that extracts data parallelism at runtimeEICHENBERGER ALEXANDRE E·Filed 2012·Granted Jul 4, 2017·0 cites·20 claims
- 4450US8862827B2Efficient multi-level software cache using SIMD vector permute functionalityFLACHS BRIAN·Filed 2009·Granted Oct 14, 2014·0 cites·25 claims
- 4550US8583905B2Runtime extraction of data parallelismEICHENBERGER ALEXANDRE E·Filed 2012·Granted Nov 12, 2013·0 cites·17 claims
- 4649US8230136B2Multithreaded programmable direct memory access engineFLACHS BRIAN K·Filed 2010·Granted Jul 24, 2012·0 cites·21 claims
- 4747US8677101B2Method and apparatus for cooperative software multitasking in a processor system with a partitioned register fileFLACHS BRIAN·Filed 2007·Granted Mar 18, 2014·0 cites·15 claims
- 4847US2011320786A1Dynamically Rewriting Branch Instructions in Response to Cache Line EvictionCHEN TONG·Filed 2010·Application pending·0 cites
- 4946US7836222B2System and method for tracking messages between a processing unit and an external deviceIBM·Filed 2003·Granted Nov 16, 2010·0 cites·16 claims
- 5046US7170316B2Programmable logic array latchIBM·Filed 2004·Granted Jan 30, 2007·3 cites·16 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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