Inventor · disambiguated record
Ravi Sundaresan
Also filed as: SUNDARESAN RAVI
29 granted patents·1 pending application·1,379 citations·filing 1996–2002
98Inventor score
Top patents by PatentIndex Score
30 records- 0197US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 0296US6461900B1Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·141 cites·22 claims
- 0396US6261935B1Method of forming contact to polysilicon gate for MOS devicesCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 17, 2001·216 cites·28 claims
- 0494US6747314B2Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 8, 2004·93 cites·11 claims
- 0594US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 0691US6406945B1Method for forming a transistor gate dielectric with high-K and low-K regionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 18, 2002·59 cites·17 claims
- 0791US6403485B1Method to form a low parasitic capacitance pseudo-SOI CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·66 cites·27 claims
- 0889US6417056B1Method to form low-overlap-capacitance transistors by forming microtrench at the gate edgeCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·51 cites·27 claims
- 0989US6306715B1Method to form smaller channel with CMOS device by isotropic etching of the gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 23, 2001·46 cites·14 claims
- 1088US6511884B1Method to form and/or isolate vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 28, 2003·48 cites·27 claims
- 1188US6468877B1Method to form an air-gap under the edges of a gate electrode by using disposable spacer/linerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·53 cites·21 claims
- 1287US6436770B1Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·45 cites·19 claims
- 1385US6759717B2CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistorST MICROELECTRONICS INC·Filed 2001·Granted Jul 6, 2004·35 cites·16 claims
- 1485US6372569B1Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performanceCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 16, 2002·47 cites·27 claims
- 1584US6475916B1Method of patterning gate electrode with ultra-thin gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 5, 2002·37 cites·24 claims
- 1683US6709934B2Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·26 cites·10 claims
- 1776US6455377B1Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)CHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·21 cites·35 claims
- 1872US6461887B1Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 8, 2002·18 cites·21 claims
- 1972US6380088B1Method to form a recessed source drain on a trench side wall with a replacement gate techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 30, 2002·19 cites·29 claims
- 2069US6303449B1Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMPCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·12 cites·11 claims
- 2164US6544824B1Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channelCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·12 cites·26 claims
- 2262US6436774B1Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 20, 2002·8 cites·10 claims
- 2358US6541327B1Method to form self-aligned source/drain CMOS device on insulated staircase oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 1, 2003·8 cites·9 claims
- 2456US6306714B1Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxideCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 23, 2001·8 cites·15 claims
- 2552US6440800B1Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layersCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 27, 2002·5 cites·12 claims
- 2652US6417054B1Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·5 cites·21 claims
- 2752US5652152AProcess having high tolerance to buried contact mask misalignment by using a PSG spacerCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jul 29, 1997·16 cites·23 claims
- 2848US6221709B1Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistorST MICROELECTRONICS INC·Filed 1997·Granted Apr 24, 2001·10 cites·19 claims
- 2943US5742088AProcess having high tolerance to buried contact mask misalignment by using a PSG spacerCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Apr 21, 1998·9 cites·3 claims
- 3034US2003017710A1Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive areaCHARTERED SEMICONDUCTOR MFG·Filed 2001·Application pending·0 cites
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