Inventor · disambiguated record
Peter J. Camporese
Also filed as: CAMPORESE PETER J
13 granted patents·563 citations·filing 1993–2001
94Inventor score
Technology areasG06F
Files withIBM13
Top patents by PatentIndex Score
13 records- 0192US6311313B1X-Y grid tree clock distribution network with tunable tree and grid networksIBM·Filed 1998·Granted Oct 30, 2001·196 cites·28 claims
- 0285US6487706B1Contract methodology for concurrent hierarchical designIBM·Filed 2000·Granted Nov 26, 2002·67 cites·2 claims
- 0382US6205571B1X-Y grid tree tuning methodIBM·Filed 1998·Granted Mar 20, 2001·104 cites·18 claims
- 0480US6323050B1Method for evaluating decoupling capacitor placement for VLSI chipsIBM·Filed 2000·Granted Nov 27, 2001·26 cites·17 claims
- 0576US6546529B1Method for performing coupling analysisIBM·Filed 2000·Granted Apr 8, 2003·25 cites·8 claims
- 0669US5455931AProgrammable clock tuning system and methodIBM·Filed 1993·Granted Oct 3, 1995·54 cites·32 claims
- 0765US6618843B2Method for evaluating decoupling capacitor placement for VLSI chipsIBM·Filed 2001·Granted Sep 9, 2003·9 cites·17 claims
- 0863US6618844B2Method for evaluating decoupling capacitor placement for VLSI chipsIBM·Filed 2001·Granted Sep 9, 2003·8 cites·19 claims
- 0950US6629298B1Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI designIBM·Filed 1999·Granted Sep 30, 2003·24 cites·16 claims
- 1046US6460169B1Routing program method for positioning unit pins in a hierarchically designed VLSI chipIBM·Filed 1999·Granted Oct 1, 2002·18 cites·11 claims
- 1144US6374394B1Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chipIBM·Filed 1999·Granted Apr 16, 2002·16 cites·11 claims
- 1241US6415428B1Minimal length method for positioning unit pins in a hierarchically designed VLSI chipIBM·Filed 1999·Granted Jul 2, 2002·13 cites·13 claims
- 1323US6341365B1Method for automating the placement of a repeater device in an optimal location, considering pre-defined blockages, in high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designsIBM·Filed 1999·Granted Jan 22, 2002·3 cites·14 claims
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