Inventor · disambiguated record
David B. Witt
Also filed as: WITT DAVID · WITT DAVID B
107 granted patents·3 pending applications·4,537 citations·filing 1986–2024
99Inventor score
Files withADVANCED MICRO DEVICES INC101ANALOG DEVICES INC3SIMPLEX MICRO INC2GEN MOTORS CORP1INTEL CORP1
Top patents by PatentIndex Score
110 records- 0199US5651125AHigh performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operationsADVANCED MICRO DEVICES INC·Filed 1995·Granted Jul 22, 1997·398 cites·28 claims
- 0294US5860104AData cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updatesADVANCED MICRO DEVICES INC·Filed 1995·Granted Jan 12, 1999·262 cites·14 claims
- 0394US5623627AComputer memory architecture including a replacement cacheADVANCED MICRO DEVICES INC·Filed 1993·Granted Apr 22, 1997·99 cites·21 claims
- 0492US6505292B1Processor including efficient fetch mechanism for L0 and L1 cachesADVANCED MICRO DEVICES INC·Filed 2002·Granted Jan 7, 2003·59 cites·14 claims
- 0591US6308259B1Instruction queue evaluating dependency vector in portions during different clock phasesADVANCED MICRO DEVICES INC·Filed 2000·Granted Oct 23, 2001·60 cites·19 claims
- 0689US6266752B1Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cacheADVANCED MICRO DEVICES INC·Filed 2000·Granted Jul 24, 2001·53 cites·20 claims
- 0788US6141747ASystem for store to load forwarding of individual bytes from separate store buffer entries to form a single load wordADVANCED MICRO DEVICES INC·Filed 1998·Granted Oct 31, 2000·135 cites·26 claims
- 0887US6553482B1Universal dependency vector/queue entryADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 22, 2003·40 cites·34 claims
- 0986US5689672APre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructionsADVANCED MICRO DEVICES INC·Filed 1993·Granted Nov 18, 1997·99 cites·38 claims
- 1085US6446181B1System having a configurable cache/SRAM memoryINTEL CORP·Filed 2000·Granted Sep 3, 2002·43 cites·19 claims
- 1184US6256728B1Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instructionADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 3, 2001·113 cites·25 claims
- 1284US6094716ARegister renaming in which moves are accomplished by swapping rename tagsADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 25, 2000·96 cites·22 claims
- 1384US5796973AMethod and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructionsADVANCED MICRO DEVICES INC·Filed 1997·Granted Aug 18, 1998·97 cites·47 claims
- 1483US5357626AProcessing system for providing an in circuit emulator with processor internal stateADVANCED MICRO DEVICES INC·Filed 1993·Granted Oct 18, 1994·99 cites·22 claims
- 1582US6189068B1Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycleADVANCED MICRO DEVICES INC·Filed 1999·Granted Feb 13, 2001·88 cites·15 claims
- 1682US5664136AHigh performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operationsADVANCED MICRO DEVICES INC·Filed 1996·Granted Sep 2, 1997·66 cites·27 claims
- 1780US6321326B1Prefetch instruction specifying destination functional unit and read/write access modeADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 20, 2001·25 cites·20 claims
- 1880US6256721B1Register renaming in which moves are accomplished by swapping tagsADVANCED MICRO DEVICES INC·Filed 2000·Granted Jul 3, 2001·24 cites·22 claims
- 1980US6202139B1Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processingADVANCED MICRO DEVICES INC·Filed 1998·Granted Mar 13, 2001·44 cites·39 claims
- 2080US6112293AProcessor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead resultADVANCED MICRO DEVICES INC·Filed 1998·Granted Aug 29, 2000·91 cites·21 claims
- 2180US5944815AMicroprocessor configured to execute a prefetch instruction including an access count field defining an expected number of accessADVANCED MICRO DEVICES INC·Filed 1998·Granted Aug 31, 1999·85 cites·20 claims
- 2280US5867682AHigh performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operationsADVANCED MICRO DEVICES INC·Filed 1996·Granted Feb 2, 1999·58 cites·34 claims
- 2379US5828869AMicroprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanismADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 27, 1998·73 cites·77 claims
- 2478US6393546B1Physical rename register for efficiently storing floating point, integer, condition code, and multimedia valuesADVANCED MICRO DEVICES INC·Filed 2001·Granted May 21, 2002·21 cites·19 claims
- 2578US5751981AHigh performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length formatADVANCED MICRO DEVICES INC·Filed 1996·Granted May 12, 1998·53 cites·29 claims
- 2677US5655098AHigh performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length formatADVANCED MICRO DEVICES INC·Filed 1996·Granted Aug 5, 1997·49 cites·37 claims
- 2776US6457117B1Processor configured to predecode relative control transfer instructions and replace displacements therein with a target addressADVANCED MICRO DEVICES INC·Filed 2000·Granted Sep 24, 2002·19 cites·14 claims
- 2876US5867683AMethod of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operationsADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 2, 1999·47 cites·12 claims
- 2975US6237082B1Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions receivedADVANCED MICRO DEVICES INC·Filed 2000·Granted May 22, 2001·20 cites·29 claims
- 3075US5835753AMicroprocessor with dynamically extendable pipeline stages and a classifying circuitADVANCED MICRO DEVICES INC·Filed 1995·Granted Nov 10, 1998·72 cites·23 claims
- 3174US5805912AMicroprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessorADVANCED MICRO DEVICES INC·Filed 1993·Granted Sep 8, 1998·54 cites·63 claims
- 3273US5987561ASuperscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycleADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 16, 1999·60 cites·20 claims
- 3373US5768555AReorder buffer employing last in buffer and last in line bitsADVANCED MICRO DEVICES INC·Filed 1997·Granted Jun 16, 1998·53 cites·21 claims
- 3473US5059818ASelf-regulating clock generatorADVANCED MICRO DEVICES INC·Filed 1990·Granted Oct 22, 1991·63 cites·15 claims
- 3572US6212622B1Mechanism for load block on store address generationADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 3, 2001·59 cites·18 claims
- 3670US6212623B1Universal dependency vector/queue entryADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 3, 2001·50 cites·20 claims
- 3770US6088789APrefetch instruction specifying destination functional unit and read/write access modeADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 11, 2000·49 cites·23 claims
- 3869US6279101B1Instruction decoder/dispatchADVANCED MICRO DEVICES INC·Filed 1995·Granted Aug 21, 2001·56 cites·87 claims
- 3969US6247106B1Processor configured to map logical register numbers to physical register numbers using virtual register numbersADVANCED MICRO DEVICES INC·Filed 2000·Granted Jun 12, 2001·12 cites·19 claims
- 4069US5623619ALinearly addressable microprocessor cacheADVANCED MICRO DEVICES INC·Filed 1995·Granted Apr 22, 1997·42 cites·45 claims
- 4168US6381689B2Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instructionADVANCED MICRO DEVICES INC·Filed 2001·Granted Apr 30, 2002·9 cites·18 claims
- 4268US5878245AHigh performance load/store functional unit and data cacheADVANCED MICRO DEVICES INC·Filed 1993·Granted Mar 2, 1999·44 cites·28 claims
- 4367US6393549B1Instruction alignment unit for routing variable byte-length instructionsADVANCED MICRO DEVICES INC·Filed 1999·Granted May 21, 2002·43 cites·11 claims
- 4467US6161167AFully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU groupADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 12, 2000·50 cites·15 claims
- 4567US6157986AFast linear tag validation unit for use in microprocessorADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 5, 2000·50 cites·18 claims
- 4667US6018798AFloating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycleADVANCED MICRO DEVICES INC·Filed 1997·Granted Jan 25, 2000·50 cites·20 claims
- 4766US7120781B1General purpose register file architecture for aligned simdANALOG DEVICES INC·Filed 2000·Granted Oct 10, 2006·12 cites·35 claims
- 4866US5875324ASuperscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clockADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 23, 1999·47 cites·26 claims
- 4966US5157780AMaster-slave checking systemADVANCED MICRO DEVICES INC·Filed 1990·Granted Oct 20, 1992·46 cites·11 claims
- 5065US6122727ASymmetrical instructions queue for high clock frequency schedulingADVANCED MICRO DEVICES INC·Filed 1998·Granted Sep 19, 2000·39 cites·20 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
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