Inventor · disambiguated record
Ashish Pancholy
Also filed as: PANCHOLY ASHISH · PANCHOLY ASHISH S
22 granted patents·543 citations·filing 1995–2006
96Inventor score
Top patents by PatentIndex Score
22 records- 0188US6683815B1Magnetic memory cell and method for assigning tunable writing currentsSILICON MAGNETIC SYSTEMS·Filed 2002·Granted Jan 27, 2004·46 cites·21 claims
- 0287US6262937B1Synchronous random access memory having a read/write address bus and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jul 17, 2001·57 cites·14 claims
- 0386US6388927B1Direct bit line-bit line defect detection test mode for SRAMCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted May 14, 2002·52 cites·22 claims
- 0481US6385128B1Random access memory having a read/write address bus and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted May 7, 2002·25 cites·6 claims
- 0581US6292403B1Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the methodCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Sep 18, 2001·26 cites·20 claims
- 0681US6069839ACircuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the methodCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted May 30, 2000·40 cites·22 claims
- 0779US5936977AScan path circuitry including a programmable delay circuitCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Aug 10, 1999·40 cites·26 claims
- 0878US6286118B1Scan path circuitry including a programmable delay circuitCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Sep 4, 2001·37 cites·20 claims
- 0975US6115836AScan path circuitry for programming a variable clock pulse widthCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Sep 5, 2000·40 cites·25 claims
- 1075US6006347ATest mode features for synchronous pipelined memoriesCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Dec 21, 1999·38 cites·16 claims
- 1170US5864251AMethod and apparatus for self-resetting logic circuitryCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Jan 26, 1999·24 cites·18 claims
- 1268US5953285AScan path circuitry including an output register having a flow through modeCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Sep 14, 1999·28 cites·22 claims
- 1366US6862215B1MRAM data line configuration and method of operationSILICON MAGNETIC SYSTEMS·Filed 2002·Granted Mar 1, 2005·16 cites·20 claims
- 1466US6262936B1Random access memory having independent read port and write port and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jul 17, 2001·21 cites·18 claims
- 1557US6664810B1Multi-level programmable voltage control and output buffer with selectable operating voltageCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Dec 16, 2003·6 cites·27 claims
- 1656US6359316B1Method and apparatus to prevent latch-up in CMOS devicesCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Mar 19, 2002·18 cites·19 claims
- 1751US6775191B1Memory circuit with selective address pathSILICON MAGNETIC SYSTEMS·Filed 2002·Granted Aug 10, 2004·6 cites·20 claims
- 1848US6639831B1Localized MRAM data line and method of operationSILICON MAGNETIC SYSTEMS·Filed 2002·Granted Oct 28, 2003·6 cites·20 claims
- 1947US7809035B2Eye-safe laser navigation sensorCYPRESS SEMICONDUCTOR CORP·Filed 2006·Granted Oct 5, 2010·0 cites·22 claims
- 2047US6445645B2Random access memory having independent read port and write port and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Sep 3, 2002·4 cites·5 claims
- 2143US6380762B1Multi-level programmable voltage control and output buffer with selectable operating voltageCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Apr 30, 2002·6 cites·11 claims
- 2243US5903174AMethod and apparatus for reducing skew among input signals within an integrated circuitCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted May 11, 1999·7 cites·20 claims
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