Inventor · disambiguated record
Pradeep Nagarajan
Also filed as: NAGARAJAN PRADEEP · NAGARAJAN PRADEEP GANESAN
14 granted patents·1 pending application·161 citations·filing 2008–2023
92Inventor score
Top patents by PatentIndex Score
15 records- 0196US9711189B1On-die input reference voltage with self-calibrating duty cycle correctionWANG BONNIE I·Filed 2011·Granted Jul 18, 2017·37 cites·12 claims
- 0293US8565034B1Variation compensation circuitry for memory interfaceLU SEAN SHAU-TU·Filed 2011·Granted Oct 22, 2013·31 cites·20 claims
- 0390US10084591B1SERDES built-in sinusoidal jitter injectionORACLE INT CORP·Filed 2017·Granted Sep 25, 2018·13 cites·19 claims
- 0490US8787097B1Circuit design technique for DQS enable/disable calibrationCHONG YAN·Filed 2011·Granted Jul 22, 2014·14 cites·19 claims
- 0587US8624647B2Duty cycle correction circuit for memory interfaces in integrated circuitsCHONG YAN·Filed 2010·Granted Jan 7, 2014·9 cites·20 claims
- 0687US7893739B1Techniques for providing multiple delay paths in a delay circuitALTERA CORP·Filed 2009·Granted Feb 22, 2011·13 cites·22 claims
- 0786US8237475B1Techniques for generating PVT compensated phase offset to improve accuracy of a locked loopNAGARAJAN PRADEEP·Filed 2008·Granted Aug 7, 2012·16 cites·25 claims
- 0885US11138126B2Testing hierarchical address translation with context switching and overwritten table definition dataADVANCED RISC MACH LTD·Filed 2019·Granted Oct 5, 2021·4 cites·12 claims
- 0984US8847626B1Circuits and methods for providing clock signalsALTERA CORP·Filed 2013·Granted Sep 30, 2014·6 cites·21 claims
- 1080US9158873B1Circuit design technique for DQS enable/disable calibrationALTERA CORP·Filed 2014·Granted Oct 13, 2015·5 cites·19 claims
- 1173US8680905B1Digital PVT compensation for delay chainNAGARAJAN PRADEEP·Filed 2012·Granted Mar 25, 2014·4 cites·20 claims
- 1273US8130016B2Techniques for providing reduced duty cycle distortionNAGARAJAN PRADEEP·Filed 2009·Granted Mar 6, 2012·8 cites·20 claims
- 1356US9059716B1Digital PVT compensation for delay chainALTERA CORP·Filed 2014·Granted Jun 16, 2015·1 cites·20 claims
- 1453US2024031457A1Programmable Device-Based Accelerator Framework for Virtualized EnvironmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 1544US8159277B1Techniques for providing multiple delay paths in a delay circuitNAGARAJAN PRADEEP·Filed 2011·Granted Apr 17, 2012·0 cites·20 claims
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