Inventor · disambiguated record
Thuong Quang Truong
Also filed as: TRUONG THUONG · TRUONG THUONG Q · TRUONG THUONG QUANG
49 granted patents·13 pending applications·437 citations·filing 2001–2016
98Inventor score
Top patents by PatentIndex Score
62 records- 0194US7386636B2System and method for communicating command parameters between a processor and a memory flow controllerIBM·Filed 2005·Granted Jun 10, 2008·36 cites·22 claims
- 0291US7546393B2System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groupsIBM·Filed 2007·Granted Jun 9, 2009·23 cites·7 claims
- 0389US8489787B2Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processorsADAR ETAI·Filed 2010·Granted Jul 16, 2013·14 cites·14 claims
- 0489US6820143B2On-chip data transfer in multi-processor systemIBM·Filed 2002·Granted Nov 16, 2004·58 cites·24 claims
- 0588US6760819B2Symmetric multiprocessor coherence mechanismIBM·Filed 2001·Granted Jul 6, 2004·56 cites·21 claims
- 0683US7869459B2Communicating instructions and data between a processor and external devicesIBM·Filed 2008·Granted Jan 11, 2011·9 cites·41 claims
- 0783US6981072B2Memory management in multiprocessor systemIBM·Filed 2003·Granted Dec 27, 2005·34 cites·24 claims
- 0882US7778271B2Method for communicating instructions and data between a processor and external devicesIBM·Filed 2005·Granted Aug 17, 2010·9 cites·1 claims
- 0981US8589922B2Performance monitor design for counting events generated by thread groupsADAR ETAI·Filed 2010·Granted Nov 19, 2013·7 cites·13 claims
- 1079US7669013B2Directory for multi-node coherent busIBM·Filed 2007·Granted Feb 23, 2010·9 cites·20 claims
- 1178US7200688B2System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA commandIBM·Filed 2003·Granted Apr 3, 2007·21 cites·15 claims
- 1278US7093080B2Method and apparatus for coherent memory structure of heterogeneous processor systemsIBM·Filed 2003·Granted Aug 15, 2006·25 cites·20 claims
- 1375US7103748B2Memory management for real-time applicationsIBM·Filed 2002·Granted Sep 5, 2006·21 cites·14 claims
- 1474US7613841B2Systems and methods for reducing data storage in devices using multi-phase data transactionsTOSHIBA KK·Filed 2006·Granted Nov 3, 2009·6 cites·20 claims
- 1573US7814281B2Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environmentIBM·Filed 2006·Granted Oct 12, 2010·2 cites·20 claims
- 1670US7519780B2System and method for reducing store latency in symmetrical multiprocessor systemsIBM·Filed 2006·Granted Apr 14, 2009·5 cites·35 claims
- 1769US7055004B2Pseudo-LRU for a locking cacheIBM·Filed 2003·Granted May 30, 2006·13 cites·24 claims
- 1867US8296520B2System and method for optimizing neighboring cache usage in a multiprocessor environmentLE HIEN MINH·Filed 2007·Granted Oct 23, 2012·6 cites·20 claims
- 1966US8601193B2Performance monitor design for instruction profiling using shared countersADAR ETAI·Filed 2010·Granted Dec 3, 2013·2 cites·19 claims
- 2066US7243200B2Establishing command order in an out of order DMA command queueIBM·Filed 2004·Granted Jul 10, 2007·11 cites·17 claims
- 2165US7114042B2Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environmentIBM·Filed 2003·Granted Sep 26, 2006·8 cites·14 claims
- 2264US8024489B2System for communicating command parameters between a processor and a memory flow controllerIBM·Filed 2008·Granted Sep 20, 2011·2 cites·20 claims
- 2364US7836257B2System and method for cache line replacement selection in a multiprocessor environmentIBM·Filed 2007·Granted Nov 16, 2010·3 cites·16 claims
- 2464US7225277B2Proxy direct memory accessIBM·Filed 2003·Granted May 29, 2007·12 cites·24 claims
- 2562US7818509B2Combined response cancellation for load commandIBM·Filed 2007·Granted Oct 19, 2010·2 cites·11 claims
- 2662US7114035B2Software-controlled cache set management with software-generated class identifiersIBM·Filed 2003·Granted Sep 26, 2006·8 cites·19 claims
- 2761US7089373B2Shadow register to enhance lock acquisitionIBM·Filed 2003·Granted Aug 8, 2006·8 cites·44 claims
- 2859US7725660B2Directory for multi-node coherent busIBM·Filed 2007·Granted May 25, 2010·1 cites·20 claims
- 2959US7290107B2Direct deposit using locking cacheIBM·Filed 2004·Granted Oct 30, 2007·5 cites·17 claims
- 3057US8397029B2System and method for cache coherency in a multiprocessor systemNICHOLAS RICHARD·Filed 2007·Granted Mar 12, 2013·1 cites·20 claims
- 3157US7657667B2Method to provide cache management commands for a DMA controllerIBM·Filed 2004·Granted Feb 2, 2010·5 cites·18 claims
- 3257US7356713B2Method and apparatus for managing the power consumption of a data processing systemIBM·Filed 2003·Granted Apr 8, 2008·4 cites·18 claims
- 3355US6961820B2System and method for identifying and accessing streaming data in a locked portion of a cacheIBM·Filed 2003·Granted Nov 1, 2005·4 cites·23 claims
- 3453US8015565B2Preventing livelocks in processor selection of load requestsIBM·Filed 2005·Granted Sep 6, 2011·1 cites·14 claims
- 3553US7721123B2Method and apparatus for managing the power consumption of a data processing systemIBM·Filed 2008·Granted May 18, 2010·0 cites·19 claims
- 3653US7290106B2Method for processor to use locking cache as part of system memoryIBM·Filed 2004·Granted Oct 30, 2007·2 cites·14 claims
- 3752US7725618B2Memory barriers primitives in an asymmetric heterogeneous multiprocessor environmentIBM·Filed 2004·Granted May 25, 2010·2 cites·20 claims
- 3852US7596665B2Mechanism for a processor to use locking cache as part of system memoryIBM·Filed 2007·Granted Sep 29, 2009·0 cites·18 claims
- 3952US7590802B2Direct deposit using locking cacheIBM·Filed 2007·Granted Sep 15, 2009·0 cites·16 claims
- 4051US7877550B2Bus controller initiated write-through mechanism with hardware automatically generated clean commandIBM·Filed 2008·Granted Jan 25, 2011·0 cites·16 claims
- 4150US9594713B2Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Granted Mar 14, 2017·0 cites·20 claims
- 4250US7353341B2System and method for canceling write back operation during simultaneous snoop push or snoop kill operation in write back cachesIBM·Filed 2004·Granted Apr 1, 2008·2 cites·18 claims
- 4346US2015074357A1Direct snoop interventionQUALCOMM INC·Filed 2014·Application pending·0 cites
- 4446US2005111478A1Distributed control load shaping method and apparatusSONY COMPUTER ENTERTAINMENT INC·Filed 2003·Application pending·0 cites
- 4545US7472229B2Bus controller initiated write-through mechanismIBM·Filed 2004·Granted Dec 30, 2008·0 cites·18 claims
- 4645US2008091866A1Maintaining forward progress in a shared L2 by detecting and breaking up requestor starvationIBM·Filed 2006·Application pending·0 cites
- 4745US2006015689A1Implementation and management of moveable buffers in cache systemSONY COMPUTER ENTERTAINMENT INC·Filed 2004·Application pending·0 cites
- 4845US2008065855A1DMAC Address Translation Miss Handling MechanismKING MATTHEW E·Filed 2006·Application pending·0 cites
- 4945US2005120185A1Methods and apparatus for efficient multi-taskingIBM·Filed 2003·Application pending·0 cites
- 5044US7484052B2Distributed address arbitration scheme for symmetrical multiprocessor systemIBM·Filed 2005·Granted Jan 27, 2009·0 cites·10 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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