Inventor · disambiguated record
Ashish V. Choubal
Also filed as: CHOUBAL ASHISH · CHOUBAL ASHISH V
33 granted patents·3 pending applications·240 citations·filing 1997–2023
97Inventor score
Top patents by PatentIndex Score
36 records- 0192US9910470B2Controlling telemetry data communication in a processorINTEL CORP·Filed 2015·Granted Mar 6, 2018·10 cites·16 claims
- 0292US9823719B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2013·Granted Nov 21, 2017·11 cites·21 claims
- 0390US9250901B2Execution context swap between heterogeneous functional hardware unitsSODHI INDER M·Filed 2013·Granted Feb 2, 2016·15 cites·25 claims
- 0489US10429913B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2018·Granted Oct 1, 2019·4 cites·20 claims
- 0589US10409346B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2018·Granted Sep 10, 2019·4 cites·20 claims
- 0689US10146283B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2017·Granted Dec 4, 2018·4 cites·20 claims
- 0789US9710041B2Masking a power state of a core of a processorINTEL CORP·Filed 2015·Granted Jul 18, 2017·7 cites·21 claims
- 0885US11157052B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2019·Granted Oct 26, 2021·2 cites·20 claims
- 0983US7165144B2Managing input/output (I/O) requests in a cache memory systemINTEL CORP·Filed 2004·Granted Jan 16, 2007·43 cites·35 claims
- 1081US8984311B2Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizingMOSES JAIDEEP·Filed 2011·Granted Mar 17, 2015·10 cites·18 claims
- 1180US12314114B2Current control for a multicore processorINTEL CORP·Filed 2023·Granted May 27, 2025·0 cites·11 claims
- 1280US9335813B2Method and system for run-time reallocation of leakage current and dynamic power supply currentINTEL CORP·Filed 2013·Granted May 10, 2016·5 cites·18 claims
- 1376US9026817B2Joint optimization of processor frequencies and system sleep statesMIN ALEXANDER W·Filed 2012·Granted May 5, 2015·5 cites·30 claims
- 1475US11687135B2Controlling power delivery to a processor via a bypassTAHOE RES LTD·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 1574US11762449B2Current control for a multicore processorINTEL CORP·Filed 2021·Granted Sep 19, 2023·0 cites·22 claims
- 1674US10613611B2Current control for a multicore processorINTEL CORP·Filed 2016·Granted Apr 7, 2020·1 cites·24 claims
- 1774US9727345B2Method for booting a heterogeneous system and presenting a symmetric core viewINTEL CORP·Filed 2013·Granted Aug 8, 2017·3 cites·17 claims
- 1872US11320888B2All-digital closed loop voltage generatorINTEL CORP·Filed 2018·Granted May 3, 2022·2 cites·25 claims
- 1972US7580406B2Remote direct memory access segment generation by a network controllerINTEL CORP·Filed 2004·Granted Aug 25, 2009·17 cites·44 claims
- 2071US9665153B2Selecting a low power state based on cache flush latency determinationINTEL CORP·Filed 2014·Granted May 30, 2017·2 cites·17 claims
- 2171US5805878AMethod and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointerINTEL CORP·Filed 1997·Granted Sep 8, 1998·64 cites·33 claims
- 2268US8352770B2Method, system and apparatus for low-power storage of processor context informationINTEL CORP·Filed 2009·Granted Jan 8, 2013·3 cites·18 claims
- 2367US11237615B2Current control for a multicore processorINTEL CORP·Filed 2020·Granted Feb 1, 2022·0 cites·22 claims
- 2467US7761529B2Method, system, and program for managing memory requests by devicesINTEL CORP·Filed 2004·Granted Jul 20, 2010·17 cites·48 claims
- 2563US7877619B2Power mode control method and circuitryRACHAKONDA RAMANA·Filed 2007·Granted Jan 25, 2011·3 cites·20 claims
- 2661US10963038B2Selecting a low power state based on cache flush latency determinationINTEL CORP·Filed 2019·Granted Mar 30, 2021·0 cites·20 claims
- 2758US10374584B1Low power retention flip-flop with level-sensitive scan circuitryINTEL CORP·Filed 2018·Granted Aug 6, 2019·0 cites·19 claims
- 2857US10198065B2Selecting a low power state based on cache flush latency determinationINTEL CORP·Filed 2017·Granted Feb 5, 2019·0 cites·19 claims
- 2957US8392728B2Reducing idle leakage power in an ICHACKING LANCE·Filed 2006·Granted Mar 5, 2013·2 cites·4 claims
- 3057US7562158B2Message context based TCP transmissionINTEL CORP·Filed 2004·Granted Jul 14, 2009·4 cites·18 claims
- 3156US10503517B2Method for booting a heterogeneous system and presenting a symmetric core viewINTEL CORP·Filed 2017·Granted Dec 10, 2019·0 cites·15 claims
- 3254US8719612B2Method, system and apparatus for low-power storage of processor context informationINTEL CORP·Filed 2013·Granted May 6, 2014·0 cites·15 claims
- 3352US7870268B2Method, system, and program for managing data transmission through a networkINTEL CORP·Filed 2003·Granted Jan 11, 2011·2 cites·30 claims
- 3444US2005021558A1Network protocol off-load engine memory managementFiled 2003·Application pending·0 cites
- 3543US2006004983A1Method, system, and program for managing memory options for devicesTSAO GARY Y·Filed 2004·Application pending·0 cites
- 3642US2006004941A1Method, system, and program for accessesing a virtualized data structure table in cacheSHAH HEMAL V·Filed 2004·Application pending·0 cites
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