Inventor · disambiguated record
Terence J. Lohman
Also filed as: LOHMAN TERENCE · LOHMAN TERENCE J · LOHMAN TERENCE JOSEPH
22 granted patents·1 pending application·1,177 citations·filing 1991–2013
97Inventor score
Top patents by PatentIndex Score
23 records- 0195US7249210B2Bus access arbitration schemeQUALCOMM INC·Filed 2005·Granted Jul 24, 2007·58 cites·34 claims
- 0291US5396602AArbitration logic for multiple bus computer systemIBM·Filed 1993·Granted Mar 7, 1995·164 cites·20 claims
- 0389US5450551ASystem direct memory access (DMA) support logic for PCI based computer systemIBM·Filed 1993·Granted Sep 12, 1995·140 cites·19 claims
- 0487US5381538ADMA controller including a FIFO register and a residual register for data buffering and having different operating modesIBM·Filed 1991·Granted Jan 10, 1995·130 cites·14 claims
- 0586US5548786ADynamic bus sizing of DMA transfersIBM·Filed 1994·Granted Aug 20, 1996·128 cites·10 claims
- 0680US5615217ABoundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and componentsIBM·Filed 1994·Granted Mar 25, 1997·55 cites·13 claims
- 0779US5265211AArbitration control logic for computer system having dual bus architectureIBM·Filed 1992·Granted Nov 23, 1993·84 cites·26 claims
- 0876US5255374ABus interface logic for computer system having dual bus architectureIBM·Filed 1992·Granted Oct 19, 1993·74 cites·14 claims
- 0974US5644729ABidirectional data buffer for a bus-to-bus interface unit in a computer systemIBM·Filed 1994·Granted Jul 1, 1997·65 cites·11 claims
- 1072US5544346ASystem having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a busIBM·Filed 1994·Granted Aug 6, 1996·58 cites·11 claims
- 1171US8107492B2Cooperative writes over the address channel of a busHOFMANN RICHARD GERARD·Filed 2006·Granted Jan 31, 2012·4 cites·35 claims
- 1269US5333274AError detection and recovery in a DMA controllerIBM·Filed 1991·Granted Jul 26, 1994·52 cites·15 claims
- 1366US7822903B2Single bus command having transfer information for transferring data in a processing systemQUALCOMM INC·Filed 2006·Granted Oct 26, 2010·3 cites·30 claims
- 1464US8675679B2Cooperative writes over the address channel of a busHOFMANN RICHARD GERARD·Filed 2011·Granted Mar 18, 2014·1 cites·66 claims
- 1564US5621897AMethod and apparatus for arbitrating for a bus to enable split transaction bus protocolsIBM·Filed 1995·Granted Apr 15, 1997·48 cites·35 claims
- 1659US8880829B2Method and apparatus for efficient, low-latency, streaming memory copiesQUALCOMM INNOVATION CT INC·Filed 2012·Granted Nov 4, 2014·1 cites·33 claims
- 1759US8108563B2Auxiliary writes over address channelHOFMANN RICHARD GERARD·Filed 2006·Granted Jan 31, 2012·1 cites·39 claims
- 1859US5555413AComputer system and method with integrated level and edge interrupt requests at the same interrupt priorityIBM·Filed 1995·Granted Sep 10, 1996·41 cites·33 claims
- 1956US5239631ACpu bus allocation controlIBM·Filed 1991·Granted Aug 24, 1993·31 cites·17 claims
- 2054US5301282AControlling bus allocation using arbitration holdIBM·Filed 1991·Granted Apr 5, 1994·26 cites·26 claims
- 2151US8521914B2Auxiliary writes over address channelHOFMANN RICHARD GERARD·Filed 2011·Granted Aug 27, 2013·0 cites·49 claims
- 2241US2013232304A1Accelerated interleaved memory data transfers in microprocessor-based systems, and related devices, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2338US5551009AExpandable high performance FIFO design which includes memory cells having respective cell multiplexorsIBM·Filed 1993·Granted Aug 27, 1996·13 cites·15 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →