Inventor

O'CONNOR JAMES MICHAEL

US55 patents

⚠️ This page may combine multiple inventors who share the name “O'CONNOR JAMES MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

O'CONNOR JAMES MICHAEL

SUN MICROSYSTEMS INC

Method frame storage using multiple memory circuits

Generation isolation system and method for garbage collection

Instruction folding for a stack-based machine

Hardware virtual machine instruction processor

Processor with accelerated array access bounds checking

Write barrier system and method for trapping garbage collection page boundary crossing pointer stores

Process of executing a method on a stack-based processor

Stack management unit and method for a processor having a stack

Write barrier system and method including pointer-specific instruction variant replacement mechanism

Processor for executing instruction sets received from a network or from a local memory

Bounded-pause time garbage collection system and method including write barrier associated with source and target instances of a partially relocated object

Bounded-pause time garbage collection system and method including write barrier associated with a source instance of a partially relocated object

Bounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated object

Method frame storage using multiple memory circuits

Method frame storage using multiple memory circuits

Array access boundary check by executing BNDCHK instruction with comparison specifiers

Array access boundary check by executing BNDCHK instruction with comparison specifiers

Multi-stack memory architecture

Look-up switch accelerator and method of operating same

Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same

Locking of computer resources

Replicating code to eliminate a level of indirection during execution of an object oriented computer program

Locking of computer resources

Method for stack-caching method frames

Multi-stack-caching memory architecture

Method for storing method frames in multiple stacks

Locking of computer resources

NVIDIA CORP

Combined on-package and off-package memory system

Write buffer for read-write interlocks

Hierarchical network for stacked memory system

Combined on-package and off-package memory system

424 encoding schemes to reduce coupling and power noise on PAM-4 data buses

Unrelaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses

Hierarchical network for stacked memory system

Application partitioning for locality in a stacked memory system

Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O

Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses

Systems and methods for dynamic random access memory (DRAM) sub-channels

Reducing coupling and power noise on PAM-4 I/O interface

ADVANCED MICRO DEVICES INC

Prefetch kernels on a graphics processing unit

Prefetch kernels on data-parallel processors

Prefetch kernels on data-parallel processors

Method and system for asymmetrical processing with managed data affinity

ALTERA CORP

Method and system for rapid insertion of various data streams into sorted tree structures

High performance network address processor system

Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same

O'CONNOR JAMES MICHAEL

Bandwidth adaptive memory compression

System and method for low-latency data compression/decompression

NYGREN AARON J

Data bus inversion coding

MCALLISTER DAVID KIRK

Zero-bandwidth clears