Inventor · disambiguated record
Rajiv Roy
Also filed as: ROY RAJIV · ROY RAJIV K · ROY RAJIV KUMAR
22 granted patents·6 pending applications·362 citations·filing 1993–2020
95Inventor score
Files withLSI CORP13SEMICONDUCTOR TECH & INSTR INC6ADVANCED RISC MACH LTD2CADENCE DESIGN SYSTEMS INC2TEXAS INSTRUMENTS INC2
Top patents by PatentIndex Score
28 records- 0192US6118540AMethod and apparatus for inspecting a workpieceSEMICONDUCTOR TECH & INSTR INC·Filed 1997·Granted Sep 12, 2000·99 cites·17 claims
- 0291US9177633B2Bit line write assist for static random access memory architecturesLSI CORP·Filed 2014·Granted Nov 3, 2015·16 cites·19 claims
- 0388US10430215B1Method and system to transfer data between hardware emulator and host workstationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 1, 2019·11 cites·18 claims
- 0488US8923090B1Address decoding circuits for reducing address and memory enable setup timeLSI CORP·Filed 2013·Granted Dec 30, 2014·12 cites·21 claims
- 0582US9111637B1Differential latch word line assist for SRAMLSI CORP·Filed 2014·Granted Aug 18, 2015·8 cites·20 claims
- 0681US9583209B1High density memory architectureADVANCED RISC MACH LTD·Filed 2015·Granted Feb 28, 2017·9 cites·15 claims
- 0781US5956134AInspection system and method for leads of semiconductor devicesSEMICONDUCTOR TECH & INSTR INC·Filed 1998·Granted Sep 21, 1999·68 cites·30 claims
- 0872US9767870B1Voltage aware circuitryADVANCED RISC MACH LTD·Filed 2016·Granted Sep 19, 2017·6 cites·14 claims
- 0972US6765666B1System and method for inspecting bumped wafersSEMICONDUCTOR TECH & INSTR INC·Filed 2000·Granted Jul 20, 2004·18 cites·18 claims
- 1071US9177635B1Dual rail single-ended read data paths for static random access memoriesLSI CORP·Filed 2014·Granted Nov 3, 2015·4 cites·11 claims
- 1170US6252981B1System and method for selection of a reference dieSEMICONDUCTOR TECH & INSTR INC·Filed 1999·Granted Jun 26, 2001·41 cites·26 claims
- 1263US9147495B2Two-bit read-only memory cellLSI CORP·Filed 2013·Granted Sep 29, 2015·4 cites·20 claims
- 1358US9064583B2Fast access with low leakage and low power technique for read only memory devicesLSI CORP·Filed 2013·Granted Jun 23, 2015·2 cites·20 claims
- 1454US8988959B2Circuit and method for dynamically changing a trip point in a sensing inverterLSI CORP·Filed 2012·Granted Mar 24, 2015·1 cites·20 claims
- 1551US5987161AApparatus and method for identifying defective objectsTEXAS INSTRUMENTS INC·Filed 1994·Granted Nov 16, 1999·20 cites·20 claims
- 1648US5402505ASemiconductor device lead inspection systemTEXAS INSTRUMENTS INC·Filed 1993·Granted Mar 28, 1995·17 cites·11 claims
- 1746US5745593AMethod and system for inspecting integrated circuit lead burrsSEMICONDUCTOR TECH & INSTR INC·Filed 1996·Granted Apr 28, 1998·16 cites·22 claims
- 1844US11475192B1Methods and apparatus for buffered assertion reporting in emulationCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Oct 18, 2022·0 cites·20 claims
- 1943US9952041B2Assessing alignment of top and bottom ends of TSVs and characterizing microfabrication processRUDOLPH TECH INC·Filed 2014·Granted Apr 24, 2018·0 cites·9 claims
- 2040US9053761B2Circuit and method for improving sense amplifier reaction time in memory read operationsLSI CORP·Filed 2012·Granted Jun 9, 2015·0 cites·21 claims
- 2140US8264899B2Assistance in reset of data storage arrayKUMAR ASHISH·Filed 2009·Granted Sep 11, 2012·0 cites·35 claims
- 2239US2001028734A1System and method for selection of a reference dieFiled 2001·Application pending·0 cites
- 2338US5777886AProgrammable lead conditionerSEMICONDUCTOR TECH & INSTR INC·Filed 1994·Granted Jul 7, 1998·10 cites·22 claims
- 2438US2015078103A1Sensing technique for single-ended bit line memory architecturesLSI CORP·Filed 2014·Application pending·0 cites
- 2537US2015138864A1Memory architecture with alternating segments and multiple bitlinesLSI CORP·Filed 2013·Application pending·0 cites
- 2637US2015302918A1Word line decoders for dual rail static random access memoriesLSI CORP·Filed 2014·Application pending·0 cites
- 2737US2015138863A1Interleaved write assist for hierarchical bitline sram architecturesLSI CORP·Filed 2013·Application pending·0 cites
- 2836US2015138876A1Global bitline write assist for sram architecturesLSI CORP·Filed 2014·Application pending·0 cites
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