Inventor · disambiguated record
Juanita Deloach
Also filed as: DELOACH JUANITA
7 granted patents·1 pending application·56 citations·filing 2002–2007
83Inventor score
Top patents by PatentIndex Score
8 records- 0186US7422967B2Method for manufacturing a semiconductor device containing metal silicide regionsTEXAS INSTRUMENTS INC·Filed 2005·Granted Sep 9, 2008·15 cites·13 claims
- 0273US6818526B2Method for moat nitride pull back for shallow trench isolationTEXAS INSTRUMENTS INC·Filed 2002·Granted Nov 16, 2004·21 cites·7 claims
- 0372US7897513B2Method for forming a metal silicideTEXAS INSTRUMENTS INC·Filed 2007·Granted Mar 1, 2011·5 cites·19 claims
- 0465US8546259B2Nickel silicide formation for semiconductor componentsDELOACH JUANITA·Filed 2007·Granted Oct 1, 2013·3 cites·34 claims
- 0560US7320927B2In situ hardmask pullback using an in situ plasma resist trim processTEXAS INSTRUMENTS INC·Filed 2003·Granted Jan 22, 2008·11 cites·20 claims
- 0644US7670952B2Method of manufacturing metal silicide contactsTEXAS INSTRUMENTS INC·Filed 2007·Granted Mar 2, 2010·0 cites·6 claims
- 0742US6905943B2Forming a trench to define one or more isolation regions in a semiconductor structureTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 14, 2005·1 cites·7 claims
- 0837US2009020791A1Process method to fabricate cmos circuits with dual stress contact etch-stop liner layersYU SHAOFENG·Filed 2007·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →