Inventor · disambiguated record
Jay Nejedlo
Also filed as: NEJEDLO JAY · NEJEDLO JAY J · NEJEDLO JAY JOSEPH
10 granted patents·5 pending applications·188 citations·filing 2002–2015
91Inventor score
Top patents by PatentIndex Score
15 records- 0191US7437643B2Automated BIST execution scheme for a linkINTEL CORP·Filed 2005·Granted Oct 14, 2008·30 cites·10 claims
- 0287US7536267B2Built-in self test for memory interconnect testingINTEL CORP·Filed 2005·Granted May 19, 2009·18 cites·9 claims
- 0383US6826100B2Push button mode automatic pattern switching for interconnect built-in self testINTEL CORP·Filed 2003·Granted Nov 30, 2004·31 cites·17 claims
- 0480US7464307B2High performance serial bus testing methodologyINTEL CORP·Filed 2003·Granted Dec 9, 2008·26 cites·20 claims
- 0580US7047458B2Testing methodology and apparatus for interconnectsINTEL CORP·Filed 2002·Granted May 16, 2006·25 cites·22 claims
- 0676US7155370B2Reusable, built-in self-test methodology for computer systemsINTEL CORP·Filed 2003·Granted Dec 26, 2006·24 cites·14 claims
- 0774US7590504B2Graphical user interface for creation of IBIST testsASSET INTERTECH INC·Filed 2006·Granted Sep 15, 2009·11 cites·27 claims
- 0872US10198333B2Test, validation, and debug architectureTROBOUGH MARK B·Filed 2010·Granted Feb 5, 2019·6 cites·20 claims
- 0972US8868992B2Robust memory link testing using memory controllerSPRY BRYAN L·Filed 2009·Granted Oct 21, 2014·10 cites·13 claims
- 1065US7562274B2User data driven test control software application the requires no software maintenanceASSET INTERTECH INC·Filed 2006·Granted Jul 14, 2009·7 cites·39 claims
- 1142US2004193976A1Method and apparatus for interconnect built-in self test based system management failure monitoringFiled 2003·Application pending·0 cites
- 1236US2017052586A1Transparently monitoring power delivery in a processorINTEL CORP·Filed 2015·Application pending·0 cites
- 1334US2004193986A1On-die pattern generator for high speed serial interconnect built-in self testFiled 2003·Application pending·0 cites
- 1433US2005080581A1Built-in self test for memory interconnect testingFiled 2003·Application pending·0 cites
- 1533US2004117708A1Pre-announce signaling for interconnect built-in self testFiled 2003·Application pending·0 cites
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