Inventor

JUFFA NORBERT

US33 patents

⚠️ This page may combine multiple inventors who share the name “JUFFA NORBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JUFFA NORBERT

ADVANCED MICRO DEVICES INC

Method and apparatus for multi-function arithmetic

Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction

Method and apparatus for rounding in a multiplier

Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit

Method and apparatus for achieving higher frequencies of exactly rounded results

Floating point addition pipeline including extreme value, comparison and accumulate functions

Method and apparatus for rapid execution of FCOM and FSTSW

Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria

Multi-function bipartite look-up table

Bipartite look-up table with output values having minimized absolute error

Microprocessor including an efficient implemention of an accumulate instruction

Apparatus and method for superforwarding load operands in a microprocessor

Apparatus and method for executing floating-point store instructions in a microprocessor

Rapid execution of floating point load control word instructions

Apparatus and method for using checking instructions in a floating-point execution unit

Method and apparatus for calculating reciprocals and reciprocal square roots

Method and apparatus for compressing intermediate products

Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor

Floating point addition pipeline including extreme value, comparison and accumulate functions

Microprocessor including an efficient implementation of extreme value instructions

Method and apparatus for calculating a power of an operand

Microprocessor including an efficient implementation of extreme value instructions

NVIDIA CORP

Maximized memory throughput using cooperative thread arrays

Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication

Efficient matrix multiplication on a parallel processing device

Hardware/software-based mapping of CTAs to matrix tiles for efficient matrix multiplication

Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors

Graphics processing unit used for cryptographic processing

JUFFA NORBERT

Graphics processor with memory management unit and cache coherent link

Maximized memory throughput on parallel processing devices

Pipelined integer division using floating-point reciprocal

Efficient matrix multiplication on a parallel processing device

Optimized 3D lighting computations using a logarithmic number system