P

Inventor

GONZALEZ ANTONIO

US58 patents
⚠️ This page may combine multiple inventors who share the name “GONZALEZ ANTONIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

24 patents
US7434073B2Oct 7, 2008

Frequency and voltage scaling architecture

INTEL CORP219 citations99
US7194643B2Mar 20, 2007

Apparatus and method for an energy efficient clustered micro-architecture

INTEL CORP215 citations99
US7478198B2Jan 13, 2009

Multithreaded clustered microarchitecture with dynamic back-end assignment

INTEL CORP42 citations96
US7330983B2Feb 12, 2008

Temperature-aware steering mechanism

INTEL CORP78 citations96
US7930574B2Apr 19, 2011

Thread migration to improve power efficiency in a parallel processing environment

INTEL CORP28 citations92
US7814469B2Oct 12, 2010

Speculative multi-threading for instruction prefetch and/or trace pre-build

INTEL CORP13 citations92
US7458065B2Nov 25, 2008

Selection of spawning pairs for a speculative multithreaded processor

INTEL CORP24 citations91
US7814339B2Oct 12, 2010

Leakage power estimation

INTEL CORP15 citations84
US7657766B2Feb 2, 2010

Apparatus for an energy efficient clustered micro-architecture

INTEL CORP11 citations84
US7447054B2Nov 4, 2008

NBTI-resilient memory cells with NAND gates

INTEL CORP14 citations83
US7895415B2Feb 22, 2011

Cache sharing based thread control

INTEL CORP16 citations82
US7313675B2Dec 25, 2007

Register allocation technique

INTEL CORP8 citations74
US7689804B2Mar 30, 2010

Selectively protecting a register file

INTEL CORP7 citations73
US7665000B2Feb 16, 2010

Meeting point thread characterization

INTEL CORP7 citations72
US7600145B2Oct 6, 2009

Clustered variations-aware architecture

INTEL CORP7 citations72
US7558992B2Jul 7, 2009

Reducing the soft error vulnerability of stored data

INTEL CORP7 citations72
US9047014B2Jun 2, 2015

Frequency and voltage scaling architecture

INTEL CORP1 citations63
US7996617B2Aug 9, 2011

Multithreaded clustered microarchitecture with dynamic back-end assignment

INTEL CORP1 citations63
US8352812B2Jan 8, 2013

Protecting data storage structures from intermittent errors

INTEL CORP2 citations62
US7024542B2Apr 4, 2006

System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions

INTEL CORP5 citations62
US10528473B2Jan 7, 2020

Disabling cache portions during low voltage operations

INTEL CORP1 citations61
US7698512B2Apr 13, 2010

Compressing address communications between processors

INTEL CORP3 citations61
US7577015B2Aug 18, 2009

Memory content inverting to minimize NTBI effects

INTEL CORP4 citations61
US10621092B2Apr 14, 2020

Merging level cache and data cache units having indicator bits related to speculative execution

INTEL CORP1 citations60

VERA XAVIER

3 patents

WILKERSON CHRISTOPHER

3 patents

LATORRE FERNANDO

3 patents

LOPEZ PEDRO

2 patents

PARJUS JOSE ALEJANDRO

2 patents

ADDUP

2 patents

(unassigned)

1 patent

MADRILES CARLOS

1 patent

VACCO IND INC

1 patent

OLIN CORP

1 patent

GIMENO CARLOS MADRILES

1 patent

WANG HONG

1 patent

CAI QIONG

1 patent

GIBERT ENRIC

1 patent

HYDRO QUEBEC

1 patent

STAVROU KYRIAKOS A

1 patent

MAGKLIS GRIGORIOS

1 patent

Showing the top 50 of 58 patents by PatentIndex Score.