Inventor

SHAFIEE ARDESTANI ALI

US38 patents

⚠️ This page may combine multiple inventors who share the name “SHAFIEE ARDESTANI ALI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAFIEE ARDESTANI ALI

SAMSUNG ELECTRONICS CO LTD

System and method for performing computations for deep neural networks

System and method for increasing utilization of dot-product based neural network accelerator

Neural processor

Neural processor

Signed multiplication using unsigned multiplier with dynamic fine-grained operand isolation

Mixed-precision NPU tile with depth-wise convolution

Piecewise quantization for neural networks

Neural processor

Neural processor

Neural processor

Hardware channel-parallel data compression/decompression

Signed multiplication using unsigned multiplier with dynamic fine-grained operand isolation

Hardware channel-parallel data compression/decompression

Signed multiplication using unsigned multiplier with dynamic fine-grained operand isolation

Mixed-precision neural network accelerator tile with lattice fusion

System and method for increasing utilization of dot-product based neural network accelerator

System and method for performing computations for deep neural networks

Depthwise-convolution implementation on a neural processing core

SRAM-sharing for reconfigurable neural processing units

Efficiency of vision transformers with adaptive token pruning

Processor for fine-grain sparse integer and floating-point operations

Hierarchical weight preprocessing for neural network accelerator

Processor with outlier accommodation

Supporting floating point 16 (FP16) in dot product architecture

Neural-processing unit tile for shuffling queued nibbles for multiplication with non-zero weight nibbles

Low overhead implementation of Winograd for CNN with 3x3, 1x3 and 3x1 filters on weight station dot-product based CNN accelerators

Accelerating 2D convolutional layer mapping on a dot product architecture

Processor for fine-grain sparse integer and floating-point operations

Circuit for handling processing with outliers

Mixed-precision neural processing unit (NPU) using spatial fusion with load balancing

HEWLETT PACKARD ENTPR DEV LP

Vector-matrix multiplications involving negative values

Data processing using resistive memory arrays

Matrix circuits

Dot product engine with negation indicator

Processing in-memory architectures for performing logical operations

Identifying outlying values in matrices

Signal conversion using an analog-to-digital converter and reference voltage comparison

Assigning data to a resistive memory array based on a significance level