Inventor · disambiguated record
Barsneya Chakrabarti
Also filed as: CHAKRABARTI BARSNEYA
5 granted patents·1 pending application·2 citations·filing 2013–2024
63Inventor score
Technology areasG06F
Top patents by PatentIndex Score
6 records- 0165US12475231B1Hardware security checks in static verification of integrated circuit designsSYNOPSYS INC·Filed 2024·Granted Nov 18, 2025·0 cites·20 claims
- 0260US9201992B2Method and apparatus using formal methods for checking generated-clock timing definitionsSYNOPSYS INC·Filed 2014·Granted Dec 1, 2015·1 cites·16 claims
- 0358US9721058B2System and method for reactive initialization based formal verification of electronic logic designSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·16 claims
- 0444US10599800B2Formal clock network analysis, visualization, verification and generationSYNOPSYS INC·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 0543US8656328B1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2013·Granted Feb 18, 2014·0 cites·28 claims
- 0640US2015234973A1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2014·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →