Inventor · disambiguated record
Alexander L. Barr
Also filed as: BARR ALEXANDER · BARR ALEXANDER L
22 granted patents·1 pending application·972 citations·filing 1999–2020
96Inventor score
Top patents by PatentIndex Score
23 records- 0198US6838322B2Method for forming a double-gated semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 4, 2005·259 cites·21 claims
- 0297US7282402B2Method of making a dual strained channel semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 16, 2007·69 cites·19 claims
- 0397US7226833B2Semiconductor device structure and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 5, 2007·124 cites·18 claims
- 0495US7018901B1Method for forming a semiconductor device having a strained channel and a heterojunction source/drainFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 28, 2006·105 cites·24 claims
- 0595US6713381B2Method of forming semiconductor device including interconnect barrier layersMOTOROLA INC·Filed 2002·Granted Mar 30, 2004·135 cites·13 claims
- 0694US6831350B1Semiconductor structure with different lattice constant materials and method for forming the sameFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Dec 14, 2004·89 cites·21 claims
- 0787US7067868B2Double gate device having a heterojunction source/drain and strained channelFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 27, 2006·39 cites·17 claims
- 0886US7029980B2Method of manufacturing SOI template layerFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Apr 18, 2006·25 cites·17 claims
- 0984US10586865B2Dual gate metal-oxide-semiconductor field-effect transistorCIRRUS LOGIC INT SEMICONDUCTOR LTD·Filed 2017·Granted Mar 10, 2020·6 cites·46 claims
- 1081US7208357B2Template layer formationFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 24, 2007·18 cites·26 claims
- 1180US7037795B1Low RC product transistors in SOI semiconductor processFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted May 2, 2006·26 cites·17 claims
- 1272US7781840B2Semiconductor device structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 24, 2010·4 cites·6 claims
- 1372US7045432B2Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)FREESCALE SEMICONDUCTOR INC·Filed 2004·Granted May 16, 2006·14 cites·26 claims
- 1470US7205210B2Semiconductor structure having strained semiconductor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 17, 2007·16 cites·15 claims
- 1570US7163903B2Method for making a semiconductor structure using silicon germaniumFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 16, 2007·10 cites·21 claims
- 1664US7056778B2Semiconductor layer formationFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 6, 2006·7 cites·42 claims
- 1763US7160769B2Channel orientation to enhance transistor performanceFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 9, 2007·10 cites·24 claims
- 1862US6964911B2Method for forming a semiconductor device having isolation regionsFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Nov 15, 2005·10 cites·24 claims
- 1961US7811382B2Method for forming a semiconductor structure having a strained silicon layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 12, 2010·1 cites·15 claims
- 2057US7241647B2Graded semiconductor layerFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jul 10, 2007·5 cites·29 claims
- 2153US11322465B2Metal layer patterning for minimizing mechanical stress in integrated circuit packagesCIRRUS LOGIC INT SEMICONDUCTOR LTD·Filed 2020·Granted May 3, 2022·0 cites·36 claims
- 2253US7927956B2Method for making a semiconductor structure using silicon germaniumFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 19, 2011·0 cites·6 claims
- 2327US2002000665A1Semiconductor device conductive bump and interconnect barrierFiled 1999·Application pending·0 cites
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