Inventor · disambiguated record
Min-Hsiung Chiang
Also filed as: CHIANG MIN-HSIUNG
32 granted patents·3 pending applications·443 citations·filing 1997–2016
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG27TAIWAN SEMICONDUCTOR MFG CO LTD4TAIWAN SEMICONDUCTOR MANUFACTO1TZENG KUO-CHYUAN1
Top patents by PatentIndex Score
35 records- 0196US9899263B2Method of forming layout designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Feb 20, 2018·13 cites·20 claims
- 0294US9336348B2Method of forming layout designTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted May 10, 2016·13 cites·20 claims
- 0388US6656785B2MIM process for logic-based embedded RAMTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 2, 2003·49 cites·18 claims
- 0486US8901627B2Jog design in integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Dec 2, 2014·8 cites·19 claims
- 0584US9355912B2Jog design in integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted May 31, 2016·5 cites·20 claims
- 0683US6383863B1Approach to integrate salicide gate for embedded DRAM devicesTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted May 7, 2002·38 cites·22 claims
- 0777US6100116AMethod to form a protected metal fuseTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 8, 2000·51 cites·9 claims
- 0874US6849387B2Method for integrating copper process and MIM capacitor for embedded DRAMTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Feb 1, 2005·20 cites·38 claims
- 0973US6436762B1Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay marginsTAIWAN SEMICONDUCTOR MANUFACTO·Filed 2001·Granted Aug 20, 2002·19 cites·18 claims
- 1070US6365325B1Aperture width reduction method for forming a patterned photoresist layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 2, 2002·29 cites·46 claims
- 1169US6797557B2Methods and systems for forming embedded DRAM for an MIM capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 28, 2004·15 cites·9 claims
- 1269US6025279AMethod of reducing nitride and oxide peeling after planarization using an annealTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Feb 15, 2000·34 cites·19 claims
- 1368US6656786B2MIM process for logic-based embedded RAM having front end manufacturing operationTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 2, 2003·17 cites·12 claims
- 1466US7332394B2Method to reduce a capacitor depletion phenomenaTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Feb 19, 2008·2 cites·18 claims
- 1565US7208369B2Dual poly layer and method of manufactureTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Apr 24, 2007·11 cites·10 claims
- 1665US6569732B1Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cellTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted May 27, 2003·12 cites·26 claims
- 1760US6274426B1Self-aligned contact process for a crown shaped dynamic random access memory capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 14, 2001·25 cites·9 claims
- 1859US7180116B2Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Feb 20, 2007·7 cites·21 claims
- 1958US6495425B1Memory cell structure integrating self aligned contact structure with salicide gate electrode structureTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 17, 2002·8 cites·12 claims
- 2057US6020236AMethod to form capacitance node contacts with improved isolation in a DRAM processTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 1, 2000·15 cites·20 claims
- 2155US9691721B2Jog design in integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jun 27, 2017·0 cites·20 claims
- 2250US6159786AWell-controlled CMP process for DRAM technologyTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 12, 2000·16 cites·19 claims
- 2349US6808980B2Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devicesTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 26, 2004·4 cites·44 claims
- 2447US7622347B2Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 24, 2009·0 cites·27 claims
- 2547US6600228B2Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal ruleTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jul 29, 2003·2 cites·6 claims
- 2643US9570584B2Semiconductor structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 14, 2017·0 cites·18 claims
- 2743US6294456B1Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal ruleTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Sep 25, 2001·9 cites·9 claims
- 2841US2008116496A1Integrating a DRAM with an SRAM having butted contacts and resulting devicesTZENG KUO-CHYUAN·Filed 2007·Application pending·0 cites
- 2940US6077778AMethod of improving refresh time in DRAM productsTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 20, 2000·8 cites·2 claims
- 3038US6174802B1Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact depositionTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 16, 2001·7 cites·13 claims
- 3138US2005151180A1Method to reduce a capacitor depletion phenomenaTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3237US7238566B2Method of forming one-transistor memory cell and structure formed therebyTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 3, 2007·0 cites·37 claims
- 3337US2005112876A1Method to form a robust TiCI4 based CVD TiN filmFiled 2003·Application pending·0 cites
- 3432US6033999AMethod of solving contact oblique problems of an ILD layer using a rapid thermal annealTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 7, 2000·5 cites·15 claims
- 3531US6818495B1Method for forming high purity silicon oxide field oxide isolation regionFiled 1999·Granted Nov 16, 2004·1 cites·18 claims
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