Inventor · disambiguated record
Ilya K. Ganusov
Also filed as: GANUSOV ILYA · GANUSOV ILYA K
30 granted patents·14 pending applications·142 citations·filing 2006–2025
96Inventor score
Top patents by PatentIndex Score
44 records- 0192US10284185B1Selectively providing clock signals using a programmable control circuitXILINX INC·Filed 2017·Granted May 7, 2019·10 cites·20 claims
- 0291US10049177B1Circuits for and methods of reducing power consumed by routing clock signals in an integratedXILINX INC·Filed 2015·Granted Aug 14, 2018·9 cites·9 claims
- 0390US9577615B1Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clockingXILINX INC·Filed 2015·Granted Feb 21, 2017·8 cites·20 claims
- 0490US9531351B1Configurable latch circuitXILINX INC·Filed 2015·Granted Dec 27, 2016·8 cites·20 claims
- 0589US12164462B2Micro-network-on-chip and microsector infrastructureINTEL CORP·Filed 2020·Granted Dec 10, 2024·2 cites·19 claims
- 0689US10069486B1Multimode registers with pulse latchesXILINX INC·Filed 2016·Granted Sep 4, 2018·7 cites·16 claims
- 0789US9875330B2Folding duplicate instances of modules in a circuit designXILINX INC·Filed 2015·Granted Jan 23, 2018·7 cites·20 claims
- 0889US9842187B1Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit designXILINX INC·Filed 2016·Granted Dec 12, 2017·9 cites·20 claims
- 0987US9537491B1Leaf-level generation of phase-shifted clocks using programmable clock delaysXILINX INC·Filed 2015·Granted Jan 3, 2017·6 cites·19 claims
- 1086US8988125B1Circuits for and methods of routing signals in an integrated circuitXILINX INC·Filed 2013·Granted Mar 24, 2015·8 cites·20 claims
- 1186US7900078B1Asynchronous conversion circuitry apparatus, systems, and methodsACHRONIX SEMICONDUCTOR CORP·Filed 2009·Granted Mar 1, 2011·15 cites·20 claims
- 1285US9836568B1Programmable integrated circuit design flow using timing-driven pipeline analysisXILINX INC·Filed 2016·Granted Dec 5, 2017·6 cites·20 claims
- 1384US10320386B1Programmable pipeline interface circuitXILINX INC·Filed 2017·Granted Jun 11, 2019·4 cites·20 claims
- 1483US9118310B1Programmable delay circuit blockXILINX INC·Filed 2014·Granted Aug 25, 2015·6 cites·20 claims
- 1582US12248021B2Debug trace microsectorsINTEL CORP·Filed 2020·Granted Mar 11, 2025·1 cites·13 claims
- 1682US7730263B2Future execution prefetching technique and architectureCORNELL RES FOUNDATION INC·Filed 2006·Granted Jun 1, 2010·19 cites·20 claims
- 1778US9729153B1Multimode multiplexer-based circuitXILINX INC·Filed 2016·Granted Aug 8, 2017·3 cites·16 claims
- 1877US12425030B2Systems and methods for configurable interface circuitsINTEL CORP·Filed 2021·Granted Sep 23, 2025·1 cites·20 claims
- 1973US8928386B1Circuits for and methods of asychronously transmitting data in an integrated circuitXILINX INC·Filed 2013·Granted Jan 6, 2015·3 cites·17 claims
- 2073US8078899B2Asynchronous conversion circuitry apparatus, systems, and methodsMANOHAR RAJIT·Filed 2011·Granted Dec 13, 2011·3 cites·20 claims
- 2173US2025208209A1Debug trace microsectorsALTERA CORP·Filed 2025·Application pending·0 cites
- 2273US2024241650A1Logic fabric based on microsector infrastructure with data register having scan registersINTEL CORP·Filed 2024·Application pending·0 cites
- 2372US10340898B1Configurable latch circuitXILINX INC·Filed 2017·Granted Jul 2, 2019·2 cites·20 claims
- 2472US2025036591A1Micro-network-on-chip and microsector infrastructureINTEL CORP·Filed 2024·Application pending·0 cites
- 2569US2025371103A1Tensor Circuits And Methods For Multiplying With Sparse WeightsALTERA CORP·Filed 2025·Application pending·0 cites
- 2667US12411174B2Circuits and methods for configurable scan chainsINTEL CORP·Filed 2022·Granted Sep 9, 2025·0 cites·20 claims
- 2767US10230374B1Methods and circuits for preventing hold violationsXILINX INC·Filed 2016·Granted Mar 12, 2019·1 cites·16 claims
- 2866US11960734B2Logic fabric based on microsector infrastructure with data register having scan registersINTEL CORP·Filed 2020·Granted Apr 16, 2024·0 cites·20 claims
- 2963US11901896B2Soft network-on-chip overlay through a partial reconfiguration regionINTEL CORP·Filed 2021·Granted Feb 13, 2024·0 cites·20 claims
- 3063US9372953B1Increasing operating frequency of circuit designs using dynamically modified timing constraintsXILINX INC·Filed 2014·Granted Jun 21, 2016·2 cites·20 claims
- 3163US8191019B2Non-predicated to predicated conversion of asynchronous representationsMANOHAR RAJIT·Filed 2009·Granted May 29, 2012·2 cites·29 claims
- 3259US2024137026A1Techniques For Storing States Of Signals In Configurable Storage CircuitsALTERA CORP·Filed 2023·Application pending·0 cites
- 3359US2025225092A1Systems And Methods For Communication Between Integrated Circuits Using Networks-On-ChipALTERA CORP·Filed 2025·Application pending·0 cites
- 3459US2025045017A1Summation and floating point conversion of tensor resultsALTERA CORP·Filed 2024·Application pending·0 cites
- 3558US12197360B2At-speed burst sampling for user registersINTEL CORP·Filed 2021·Granted Jan 14, 2025·0 cites·20 claims
- 3655US11789641B2Three dimensional circuit systems and methods having memory hierarchiesINTEL CORP·Filed 2021·Granted Oct 17, 2023·0 cites·23 claims
- 3751US2024354480A1Programmable Logic Circuits Using Lookup Tables (LUTs) Augmented with Configurable Logic GatesCHROMCZAK JEFFREY·Filed 2024·Application pending·0 cites
- 3849US2022244867A1Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAMNG BEE YEE·Filed 2022·Application pending·0 cites
- 3948US2024348252A1Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing AbilityCHROMCZAK JEFFREY·Filed 2024·Application pending·0 cites
- 4047US2022221986A1Fabric memory network-on-chipWEBER SCOTT JEREMY·Filed 2022·Application pending·0 cites
- 4146US2025192785A1Techniques For Configurable Selection Between Hard Logic And Configurable Logic GatesALTERA CORP·Filed 2023·Application pending·0 cites
- 4245US2022012012A1Systems and Methods for Sparsity Operations in a Specialized Processing BlockLANGHAMMER MARTIN·Filed 2021·Application pending·0 cites
- 4340US9954534B2Methods and circuits for preventing hold time violationsXILINX INC·Filed 2016·Granted Apr 24, 2018·0 cites·10 claims
- 4440US2022334609A1Heterogeneous Timing Closure For Clock-Skew Scheduling or Time BorrowingINTEL CORP·Filed 2022·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →