Inventor

CHAU ROBERT

US73 patents

⚠️ This page may combine multiple inventors who share the name “CHAU ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAU ROBERT

INTEL CORP

Strained transistor integration for CMOS

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Tri-gate transistors and methods to fabricate same

Method of fabricating an ultra-narrow channel semiconductor device

Metal-gate electrode for CMOS transistor applications

Method for making a semiconductor device having a high-k gate dielectric

Non-planar MOS structure with a strained channel region

Methods for uniform doping of non-planar transistor structures

Non-planar MOS structure with a strained channel region

Double-gate transistor with enhanced carrier mobility

Method for making a semiconductor device having a metal gate electrode

Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

Method for making a semiconductor device having a high-k gate dielectric

U-gate transistors and methods of fabrication

Transistor gate electrode having conductor material layer

Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors

Plasma nitridation for reduced leakage gate dielectric layers

Transistor gate electrode having conductor material layer

Isolated Germanium nanowire on Silicon fin

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

Method of fabricating an ultra-narrow channel semiconductor device

Pre-etch implantation damage for the removal of thin film layers

Metal-gate electrode for CMOS transistor applications

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Method of making emitter trench BiCMOS using integrated dual layer emitter mask

Plasma nitridation for reduced leakage gate dielectric layers

Group III-N nanowire transistors

Group III-N nanowire transistors

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Group III-N nanowire transistors

Defect transferred and lattice mismatched epitaxial film

Metalgate electrode for PMOS transistor

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Buffer architecture formed on a semiconductor wafer

Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

Epitaxial film on nanoscale structure

Semiconductor on insulator apparatus

Transistor gate electrode having conductor material layer

Semiconductor on insulator apparatus and method

Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

THEN HAN WUI

Group III-N nanowire transistors

High voltage field effect transistors

Non-planar III-N transistor

RADOSAVLJEVIC MARKO

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

RACHMADY WILLY

Non-planar quantum well device having interfacial layer and method of forming same

PILLARISETTY RAVI

Apparatus and methods for improving parallel conduction in a quantum well device