Inventor · disambiguated record
Percy V. Gilbert
Also filed as: GILBERT PERCY · GILBERT PERCY V · GILBERT PERCY VERYON
10 granted patents·1 pending application·664 citations·filing 1993–2005
93Inventor score
Top patents by PatentIndex Score
11 records- 0196US6362071B1Method for forming a semiconductor device with an opening in a dielectric layerMOTOROLA INC·Filed 2000·Granted Mar 26, 2002·149 cites·20 claims
- 0292US6991979B2Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETsIBM·Filed 2003·Granted Jan 31, 2006·52 cites·9 claims
- 0392US5885856AIntegrated circuit having a dummy structure and method of makingMOTOROLA INC·Filed 1996·Granted Mar 23, 1999·160 cites·20 claims
- 0491US6806584B2Semiconductor device structure including multiple fets having different spacer widthsIBM·Filed 2002·Granted Oct 19, 2004·61 cites·8 claims
- 0587US5708288AThin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and methodMOTOROLA INC·Filed 1995·Granted Jan 13, 1998·74 cites·20 claims
- 0686US5349224AIntegrable MOS and IGBT devices having trench gate structurePURDUE RESEARCH FOUNDATION·Filed 1993·Granted Sep 20, 1994·68 cites·24 claims
- 0780US7091128B2Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETsIBM·Filed 2005·Granted Aug 15, 2006·6 cites·10 claims
- 0880US5744841ASemiconductor device with ESD protectionMOTOROLA INC·Filed 1997·Granted Apr 28, 1998·41 cites·23 claims
- 0965US5733794AProcess for forming a semiconductor device with ESD protectionMOTOROLA INC·Filed 1995·Granted Mar 31, 1998·22 cites·20 claims
- 1064US5773326AMethod of making an SOI integrated circuit with ESD protectionMOTOROLA INC·Filed 1996·Granted Jun 30, 1998·31 cites·13 claims
- 1133US2005048732A1Method to produce transistor having reduced gate heightIBM·Filed 2003·Application pending·0 cites
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