Inventor · disambiguated record
Robert J. Sonnelitter, Iii
Also filed as: SONNELITTER III ROBERT J · SONNELITTER ROBERT J
72 granted patents·9 pending applications·164 citations·filing 2008–2022
98Inventor score
Files withIBM55DUNN BERGER DEANNA POSTLES5AMBROLADZE EKATERINA M4BERGER DEANNA P3BERGER DEANNA POSTLES DUNN2
Top patents by PatentIndex Score
81 records- 0194US9104581B2eDRAM refresh in a high performance cache architectureFEE MICHAEL·Filed 2010·Granted Aug 11, 2015·29 cites·11 claims
- 0293US11010210B2Controller address contention assumptionIBM·Filed 2019·Granted May 18, 2021·8 cites·20 claims
- 0392US9720833B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2015·Granted Aug 1, 2017·8 cites·9 claims
- 0491US11461151B2Controller address contention assumptionIBM·Filed 2021·Granted Oct 4, 2022·2 cites·20 claims
- 0589US9892043B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2017·Granted Feb 13, 2018·5 cites·17 claims
- 0688US10055355B1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Aug 21, 2018·4 cites·1 claims
- 0788US9477613B2Position-based replacement policy for address synonym management in shared cachesIBM·Filed 2015·Granted Oct 25, 2016·9 cites·18 claims
- 0886US10795824B2Speculative data return concurrent to an exclusive invalidate requestIBM·Filed 2018·Granted Oct 6, 2020·4 cites·20 claims
- 0985US9898407B2Configuration based cache coherency protocol selectionIBM·Filed 2015·Granted Feb 20, 2018·3 cites·11 claims
- 1084US11947418B2Remote access arrayIBM·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 1184US11868259B2System coherency protocolIBM·Filed 2022·Granted Jan 9, 2024·1 cites·21 claims
- 1284US10310982B2Target cache line arbitration within a processor clusterIBM·Filed 2016·Granted Jun 4, 2019·4 cites·20 claims
- 1383US10628313B2Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cacheIBM·Filed 2017·Granted Apr 21, 2020·3 cites·8 claims
- 1481US9021240B2System and method for Controlling restarting of instruction fetching using speculative address computationsALEXANDER KHARY J·Filed 2008·Granted Apr 28, 2015·11 cites·17 claims
- 1580US9858190B2Maintaining order with parallel access data streamsIBM·Filed 2015·Granted Jan 2, 2018·3 cites·12 claims
- 1679US10628314B2Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cacheIBM·Filed 2017·Granted Apr 21, 2020·2 cites·6 claims
- 1779US9734110B2Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessingIBM·Filed 2015·Granted Aug 15, 2017·3 cites·15 claims
- 1879US8996819B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2012·Granted Mar 31, 2015·4 cites·7 claims
- 1979US8447905B2Dynamic multi-level cache including resource access fairness schemeAMBROLADZE EKATERINA M·Filed 2010·Granted May 21, 2013·6 cites·15 claims
- 2078US10649908B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Granted May 12, 2020·1 cites·17 claims
- 2178US8706970B2Dynamic cache queue allocation based on destination availabilityIBM·Filed 2012·Granted Apr 22, 2014·4 cites·6 claims
- 2278US8352687B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2010·Granted Jan 8, 2013·4 cites·7 claims
- 2377US10915461B2Multilevel cache eviction managementIBM·Filed 2019·Granted Feb 9, 2021·2 cites·14 claims
- 2477US8560803B2Dynamic cache queue allocation based on destination availabilityORF DIANA L·Filed 2010·Granted Oct 15, 2013·6 cites·11 claims
- 2575US10437729B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Oct 8, 2019·1 cites·12 claims
- 2675US9348524B1Memory controlled operations under dynamic relocation of storageIBM·Filed 2014·Granted May 24, 2016·3 cites·20 claims
- 2774US8566532B2Management of multipurpose command queues in a multilevel cache hierarchyDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Oct 22, 2013·4 cites·18 claims
- 2874US8495287B2Clock-based debugging for embedded dynamic random access memory element in a processor coreCOLLURA ADAM B·Filed 2010·Granted Jul 23, 2013·4 cites·14 claims
- 2971US8327078B2Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interfaceBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Dec 4, 2012·3 cites·15 claims
- 3070US9189415B2EDRAM refresh in a high performance cache architectureIBM·Filed 2012·Granted Nov 17, 2015·2 cites·11 claims
- 3169US7882338B2Method, system and computer program product for an implicit predicted return from a predicted subroutineIBM·Filed 2008·Granted Feb 1, 2011·4 cites·20 claims
- 3267US8447930B2Managing in-line store throughput reductionBERGER DEANNA P·Filed 2010·Granted May 21, 2013·2 cites·17 claims
- 3366US8407420B2System, apparatus and method utilizing early access to shared cache pipeline for latency reductionDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Mar 26, 2013·2 cites·19 claims
- 3465US10824565B2Configuration based cache coherency protocol selectionIBM·Filed 2019·Granted Nov 3, 2020·0 cites·20 claims
- 3565US8006039B2Method, system, and computer program product for merging dataIBM·Filed 2008·Granted Aug 23, 2011·3 cites·12 claims
- 3664US12050538B2Castout handling in a distributed cache topologyIBM·Filed 2022·Granted Jul 30, 2024·0 cites·20 claims
- 3764US2019251036A1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Application pending·0 cites
- 3864US2019251037A1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Application pending·0 cites
- 3963US7822954B2Methods, systems, and computer program products for recovering from branch prediction latencyIBM·Filed 2008·Granted Oct 26, 2010·2 cites·24 claims
- 4062US10402328B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Sep 3, 2019·0 cites·20 claims
- 4162US10394712B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 4262US8521960B2Mitigating busy time in a high performance cacheBERGER DEANNA P·Filed 2010·Granted Aug 27, 2013·1 cites·16 claims
- 4361US8447932B2Recover store data mergingBERGER DEANNA P·Filed 2010·Granted May 21, 2013·1 cites·20 claims
- 4460US9886382B2Configuration based cache coherency protocol selectionIBM·Filed 2014·Granted Feb 6, 2018·0 cites·20 claims
- 4560US9727464B2Nested cache coherency protocol in a tiered multi-node computer systemDRAPALA GARRETT MICHAEL·Filed 2014·Granted Aug 8, 2017·1 cites·16 claims
- 4660US8478920B2Controlling data stream interruptions on a shared interfaceDRAPALA GARRETT M·Filed 2010·Granted Jul 2, 2013·1 cites·16 claims
- 4758US10529396B2Preinstall of partial store cache linesIBM·Filed 2017·Granted Jan 7, 2020·1 cites·20 claims
- 4856US9298468B2Monitoring processing time in a shared pipelineIBM·Filed 2013·Granted Mar 29, 2016·0 cites·20 claims
- 4955US11620231B2Lateral persistence directory statesIBM·Filed 2021·Granted Apr 4, 2023·0 cites·25 claims
- 5055US11042483B2Efficient eviction of whole set associated cache or selected range of addressesIBM·Filed 2019·Granted Jun 22, 2021·0 cites·20 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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