Inventor · disambiguated record
Benny Eitan
Also filed as: EITAN BENNY
100 granted patents·3 pending applications·3,226 citations·filing 1991–2019
99Inventor score
Top patents by PatentIndex Score
103 records- 0198US8984043B2Multiplying and adding matricesGINZBURG BORIS·Filed 2010·Granted Mar 17, 2015·112 cites·15 claims
- 0297US6516406B1Processor executing unpack instruction to interleave data elements from two packed dataINTEL CORP·Filed 2000·Granted Feb 4, 2003·100 cites·18 claims
- 0396US8914613B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bitsSPERBER ZEEV·Filed 2011·Granted Dec 16, 2014·22 cites·27 claims
- 0496US5802336AMicroprocessor capable of unpacking packed dataINTEL CORP·Filed 1997·Granted Sep 1, 1998·172 cites·11 claims
- 0595US9672034B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bitsINTEL CORP·Filed 2013·Granted Jun 6, 2017·17 cites·21 claims
- 0694US8396915B2Processor for performing multiply-add operations on packed dataPELEG ALEXANDER·Filed 2012·Granted Mar 12, 2013·12 cites·10 claims
- 0794US5721892AMethod and apparatus for performing multiply-subtract operations on packed dataINTEL CORP·Filed 1995·Granted Feb 24, 1998·198 cites·30 claims
- 0893US8078836B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bitsSPERBER ZEEV·Filed 2007·Granted Dec 13, 2011·21 cites·37 claims
- 0993US6385634B1Method for performing multiply-add operations on packed dataINTEL CORP·Filed 1995·Granted May 7, 2002·128 cites·14 claims
- 1092US8793299B2Processor for performing multiply-add operations on packed dataINTEL CORP·Filed 2013·Granted Jul 29, 2014·8 cites·6 claims
- 1192US6631389B2Apparatus for performing packed shift operationsINTEL CORP·Filed 2000·Granted Oct 7, 2003·54 cites·34 claims
- 1292US5881275AMethod for unpacking a plurality of packed data into a result packed dataINTEL CORP·Filed 1997·Granted Mar 9, 1999·103 cites·10 claims
- 1391US7395298B2Method and apparatus for performing multiply-add operations on packed dataINTEL CORP·Filed 2003·Granted Jul 1, 2008·71 cites·18 claims
- 1490US9606770B2Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructionsINTEL CORP·Filed 2014·Granted Mar 28, 2017·9 cites·19 claims
- 1589US9465580B2Math circuit for estimating a transcendental functionPINEIRO JOSE-ALEJANDRO·Filed 2011·Granted Oct 11, 2016·24 cites·19 claims
- 1689US6035316AApparatus for performing multiply-add operations on packed dataINTEL CORP·Filed 1996·Granted Mar 7, 2000·85 cites·16 claims
- 1789US5852726AMethod and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced mannerINTEL CORP·Filed 1995·Granted Dec 22, 1998·163 cites·107 claims
- 1888US5819101AMethod for packing a plurality of packed data elements in response to a pack instructionINTEL CORP·Filed 1997·Granted Oct 6, 1998·143 cites·16 claims
- 1987US5983256AApparatus for performing multiply-add operations on packed dataINTEL CORP·Filed 1997·Granted Nov 9, 1999·68 cites·25 claims
- 2087US5675526AProcessor performing packed data multiplicationINTEL CORP·Filed 1996·Granted Oct 7, 1997·117 cites·8 claims
- 2187US5666298AMethod for performing shift operations on packed dataINTEL CORP·Filed 1996·Granted Sep 9, 1997·112 cites·14 claims
- 2286US5793661AMethod and apparatus for performing multiply and accumulate operations on packed dataINTEL CORP·Filed 1995·Granted Aug 11, 1998·131 cites·21 claims
- 2384US8185571B2Processor for performing multiply-add operations on packed dataPELEG ALEXANDER D·Filed 2009·Granted May 22, 2012·7 cites·51 claims
- 2483US8914430B2Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructionsGRADSTEIN AMIT·Filed 2010·Granted Dec 16, 2014·8 cites·17 claims
- 2583US7424505B2Method and apparatus for performing multiply-add operations on packed dataINTEL CORP·Filed 2001·Granted Sep 9, 2008·17 cites·118 claims
- 2683US6119216AMicroprocessor capable of unpacking packed data in response to a unpack instructionINTEL CORP·Filed 1999·Granted Sep 12, 2000·47 cites·17 claims
- 2783US5907842AMethod of sorting numbers to obtain maxima/minima values with orderingINTEL CORP·Filed 1995·Granted May 25, 1999·97 cites·11 claims
- 2883US5835748AMethod for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register fileINTEL CORP·Filed 1995·Granted Nov 10, 1998·114 cites·157 claims
- 2983US5701508AExecuting different instructions that cause different data type operations to be performed on single logical register fileINTEL CORP·Filed 1995·Granted Dec 23, 1997·94 cites·35 claims
- 3082US8694758B2Mixing instructions with different register sizesORENSTIEN DORON·Filed 2007·Granted Apr 8, 2014·13 cites·23 claims
- 3181US9448765B2Floating point scaling processors, methods, systems, and instructionsANDERSON CHRISTINA S·Filed 2011·Granted Sep 20, 2016·7 cites·31 claims
- 3281US7149882B2Processor with instructions that operate on different data types stored in the same single logical register fileINTEL CORP·Filed 2004·Granted Dec 12, 2006·23 cites·83 claims
- 3381US5818739AProcessor for performing shift operations on packed dataINTEL CORP·Filed 1997·Granted Oct 6, 1998·80 cites·14 claims
- 3480US8190867B2Packing two packed signed data in registers with saturationPELEG ALEXANDER·Filed 2011·Granted May 29, 2012·2 cites·13 claims
- 3580US7117232B2Method and apparatus for providing packed shift operations in a processorINTEL CORP·Filed 2005·Granted Oct 3, 2006·6 cites·28 claims
- 3680US6275834B1Apparatus for performing packed shift operationsINTEL CORP·Filed 1996·Granted Aug 14, 2001·59 cites·31 claims
- 3779US7461109B2Method and apparatus for providing packed shift operations in a processorINTEL CORP·Filed 2007·Granted Dec 2, 2008·5 cites·22 claims
- 3879US5940859AEmptying packed data state during execution of packed data instructionsINTEL CORP·Filed 1995·Granted Aug 17, 1999·65 cites·25 claims
- 3978US5983257ASystem for signal processing using multiply-add operationsINTEL CORP·Filed 1995·Granted Nov 9, 1999·86 cites·24 claims
- 4077US10275216B2Floating point scaling processors, methods, systems, and instructionsINTEL CORP·Filed 2018·Granted Apr 30, 2019·1 cites·28 claims
- 4177US10228909B2Floating point scaling processors, methods, systems, and instructionsINTEL CORP·Filed 2018·Granted Mar 12, 2019·1 cites·32 claims
- 4277US8601246B2Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination registerPELEG ALEXANDER·Filed 2002·Granted Dec 3, 2013·10 cites·72 claims
- 4375US9223572B2Interleaving half of packed data elements of size specified in instruction and stored in two source registersINTEL CORP·Filed 2012·Granted Dec 29, 2015·1 cites·29 claims
- 4475US9116687B2Packing in destination register half of each element with saturation from two source packed data registersINTEL CORP·Filed 2012·Granted Aug 25, 2015·1 cites·18 claims
- 4575US8793475B2Method and apparatus for unpacking and moving packed dataINTEL CORP·Filed 2012·Granted Jul 29, 2014·1 cites·17 claims
- 4673US6934776B2Methods and apparatus for determination of packet sizes when transferring packets via a networkINTEL CORP·Filed 2002·Granted Aug 23, 2005·17 cites·20 claims
- 4772US8626814B2Method and apparatus for performing multiply-add operations on packed dataPELEG ALEXANDER·Filed 2011·Granted Jan 7, 2014·1 cites·40 claims
- 4872US7882325B2Method and apparatus for a double width load using a single width load portINTEL CORP·Filed 2007·Granted Feb 1, 2011·5 cites·14 claims
- 4972US7451169B2Method and apparatus for providing packed shift operations in a processorINTEL CORP·Filed 2006·Granted Nov 11, 2008·3 cites·26 claims
- 5071US8725787B2Processor for performing multiply-add operations on packed dataPELEG ALEXANDER D·Filed 2012·Granted May 13, 2014·1 cites·19 claims
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