Inventor · disambiguated record
Ilya V. Neznanov
Also filed as: NEZNANOV ILYA · NEZNANOV ILYA V · NEZNANOV ILYA VLADIMIROVICH
28 granted patents·4 pending applications·73 citations·filing 2004–2014
94Inventor score
Top patents by PatentIndex Score
32 records- 0184US9337866B2Apparatus for processing signals carrying modulation-encoded parity bitsLSI CORP·Filed 2013·Granted May 10, 2016·9 cites·20 claims
- 0281US8850437B2Two-pass linear complexity task schedulerSHUTKIN YURII S·Filed 2011·Granted Sep 30, 2014·8 cites·18 claims
- 0379US7389484B2Method and apparatus for tiling memories in integrated circuit layoutLSI CORP·Filed 2005·Granted Jun 17, 2008·10 cites·20 claims
- 0474US8397143B2BCH or reed-solomon decoder with syndrome modificationNEZNANOV ILYA V·Filed 2009·Granted Mar 12, 2013·10 cites·20 claims
- 0569US7424687B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2005·Granted Sep 9, 2008·6 cites·19 claims
- 0665US8176397B2Variable redundancy reed-solomon encoderPANTELEEV PAVEL·Filed 2008·Granted May 8, 2012·7 cites·14 claims
- 0764US8656206B2Timer manager architecture based on binary heapGASANOV ELYAR E·Filed 2011·Granted Feb 18, 2014·2 cites·22 claims
- 0861US8365054B2Soft reed-solomon decoder based on error-and-erasure reed-solomon decoderLSI CORP·Filed 2009·Granted Jan 29, 2013·4 cites·20 claims
- 0958US8037432B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2008·Granted Oct 11, 2011·3 cites·12 claims
- 1057US8539009B2Parallel true random number generator architectureALISEYCHIK PAVEL A·Filed 2008·Granted Sep 17, 2013·2 cites·21 claims
- 1151US8286060B2Scheme for erasure locator polynomial calculation in error-and-erasure decoderPANTELEEV PAVEL A·Filed 2008·Granted Oct 9, 2012·2 cites·18 claims
- 1251US7823050B2Low area architecture in BCH decoderLSICorporation·Filed 2006·Granted Oct 26, 2010·3 cites·1 claims
- 1350US8621329B2Reconfigurable BCH decoderPANTELEEV PAVEL A·Filed 2011·Granted Dec 31, 2013·1 cites·20 claims
- 1450US8181096B2Configurable Reed-Solomon decoder based on modified Forney syndromesANDREEV ALEXANDER·Filed 2007·Granted May 15, 2012·2 cites·20 claims
- 1550US7155688B2Memory generation and placementLSI LOGIC CORP·Filed 2004·Granted Dec 26, 2006·1 cites·5 claims
- 1649US8527851B2System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errorsANDREEV ALEXANDER E·Filed 2008·Granted Sep 3, 2013·2 cites·12 claims
- 1746US8209589B2Reed-solomon decoder with a variable number of correctable errorsANDREEV ALEXANDRE·Filed 2008·Granted Jun 26, 2012·1 cites·18 claims
- 1844US2014223267A1Radix-4 viterbi forward error correction decodingLSI CORP·Filed 2014·Application pending·0 cites
- 1943US8923413B2Optimization of data processors with irregular patternsLSI CORP·Filed 2012·Granted Dec 30, 2014·0 cites·17 claims
- 2043US8868890B2No-delay microsequencerSHUTKIN YURII S·Filed 2011·Granted Oct 21, 2014·0 cites·20 claims
- 2142US9319181B2Parallel decoder for multiple wireless standardsSOKOLOV ANDREY P·Filed 2011·Granted Apr 19, 2016·0 cites·20 claims
- 2242US8923315B2Packet router having a hierarchical buffer structureLSI CORP·Filed 2013·Granted Dec 30, 2014·0 cites·14 claims
- 2338US8775914B2Radix-4 viterbi forward error correction decodingGASANOV ELYAR E·Filed 2011·Granted Jul 8, 2014·0 cites·18 claims
- 2438US8775893B2Variable parity encoderPANTELEEV PAVEL A·Filed 2012·Granted Jul 8, 2014·0 cites·18 claims
- 2538US8700969B2Reconfigurable encoding per multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 2638US7356743B2RRAM controller built in self test memoryLSI LOGIC CORP·Filed 2005·Granted Apr 8, 2008·0 cites·6 claims
- 2737US8699396B2Branch metrics calculation for multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 2836US2014040342A1High speed add-compare-select circuitLSI CORP·Filed 2013·Application pending·0 cites
- 2936US2014164876A1Modulation coding of parity bits generated using an error-correction codeLSI CORP·Filed 2013·Application pending·0 cites
- 3035US2012166501A1Computation of jacobian logarithm operationSOKOLOV ANDREY P·Filed 2011·Application pending·0 cites
- 3134US8938654B2Programmable circuit for high speed computation of the interleaver tables for multiple wireless standardsSOKOLOV ANDREY P·Filed 2010·Granted Jan 20, 2015·0 cites·20 claims
- 3234US8842784B2L-value generation in a decoderSOKOLOV ANDREY P·Filed 2011·Granted Sep 23, 2014·0 cites·18 claims
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