Inventor · disambiguated record
Peter A. Sandon
Also filed as: SANDON PETER · SANDON PETER A · SANDON PETER ANTHONY
46 granted patents·12 pending applications·687 citations·filing 1998–2020
98Inventor score
Top patents by PatentIndex Score
58 records- 0197US6571328B2Method and apparatus for obtaining a scalar value directly from a vector registerNINTENDO CO LTD·Filed 2001·Granted May 27, 2003·139 cites·9 claims
- 0296US7908460B2Method and apparatus for obtaining a scalar value directly from a vector registerNINTENDO CO LTD·Filed 2010·Granted Mar 15, 2011·34 cites·15 claims
- 0392US7426674B2Method of computing partial CRCsIBM·Filed 2005·Granted Sep 16, 2008·20 cites·9 claims
- 0491US7127560B2Method of dynamically controlling cache sizeIBM·Filed 2003·Granted Oct 24, 2006·81 cites·15 claims
- 0588US6794901B2Apparatus for reducing soft errors in dynamic circuitsIBM·Filed 2002·Granted Sep 21, 2004·33 cites·8 claims
- 0688US6701424B1Method and apparatus for efficient loading and storing of vectorsNINTENDO CO LTD·Filed 2000·Granted Mar 2, 2004·44 cites·6 claims
- 0787US8988139B2Self-selected variable power integrated circuitIBM·Filed 2013·Granted Mar 24, 2015·11 cites·19 claims
- 0886US6681296B2Method and apparatus for software management of on-chip cacheNINTENDO CO LTD·Filed 2001·Granted Jan 20, 2004·39 cites·12 claims
- 0985US6859862B1Method and apparatus for software management of on-chip cacheNINTENDO CO LTD·Filed 2000·Granted Feb 22, 2005·37 cites·2 claims
- 1084US7962695B2Method and system for integrating SRAM and DRAM architecture in set associative cacheIBM·Filed 2007·Granted Jun 14, 2011·14 cites·27 claims
- 1184US7949853B2Two dimensional addressing of a matrix-vector register arrayIBM·Filed 2007·Granted May 24, 2011·12 cites·14 claims
- 1284US7526698B2Error detection and correction in semiconductor structuresIBM·Filed 2006·Granted Apr 28, 2009·12 cites·12 claims
- 1381US7185215B2Machine code builder derived power consumption reductionIBM·Filed 2003·Granted Feb 27, 2007·32 cites·28 claims
- 1481US6857061B1Method and apparatus for obtaining a scalar value directly from a vector registerNINTENDO CO LTD·Filed 2000·Granted Feb 15, 2005·22 cites·8 claims
- 1580US7941772B2Dynamic critical path detector for digital logic circuit pathsIBM·Filed 2007·Granted May 10, 2011·10 cites·22 claims
- 1678US11165766B2Implementing authentication protocol for merging multiple server nodes with trusted platform modules utilizing provisioned node certificates to support concurrent node add and removeIBM·Filed 2018·Granted Nov 2, 2021·2 cites·20 claims
- 1778US7739480B2Method and apparatus for obtaining a scalar value directly from a vector registerNINTENDO CO LTD·Filed 2005·Granted Jun 15, 2010·6 cites·13 claims
- 1878US7010469B2Method of computing partial CRCsIBM·Filed 2003·Granted Mar 7, 2006·18 cites·20 claims
- 1974US10628579B2System and method for supporting secure objects using a memory access control monitorIBM·Filed 2015·Granted Apr 21, 2020·2 cites·10 claims
- 2073US8132136B2Dynamic critical path detector for digital logic circuit pathsBUETI SERAFINO·Filed 2007·Granted Mar 6, 2012·7 cites·20 claims
- 2173US8108753B2Method of computing partial CRCsANDERSON RICHARD E·Filed 2008·Granted Jan 31, 2012·6 cites·8 claims
- 2272US8024513B2Method and system for implementing dynamic refresh protocols for DRAM based cacheIBM·Filed 2007·Granted Sep 20, 2011·5 cites·20 claims
- 2372US7882302B2Method and system for implementing prioritized refresh of DRAM based cacheIBM·Filed 2007·Granted Feb 1, 2011·5 cites·20 claims
- 2471US8347019B2Structure for hardware assisted bus state transition circuit using content addressable memoriesIBM·Filed 2008·Granted Jan 1, 2013·5 cites·25 claims
- 2571US7386703B2Two dimensional addressing of a matrix-vector register arrayIBM·Filed 2003·Granted Jun 10, 2008·14 cites·6 claims
- 2669US8291357B2On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variationsBUETI SERAFINO·Filed 2007·Granted Oct 16, 2012·5 cites·20 claims
- 2767US7249358B2Method and apparatus for dynamically allocating processorsIBM·Filed 2003·Granted Jul 24, 2007·12 cites·14 claims
- 2865US8108609B2Structure for implementing dynamic refresh protocols for DRAM based cacheBARTH JOHN E·Filed 2008·Granted Jan 31, 2012·5 cites·10 claims
- 2964US8756543B2Verifying data intensive state transition machines related applicationPARUTHI VIRESH·Filed 2011·Granted Jun 17, 2014·2 cites·20 claims
- 3064US7496731B2Two dimensional addressing of a matrix-vector register arrayIBM·Filed 2007·Granted Feb 24, 2009·2 cites·13 claims
- 3163US6694417B1Write pipeline and method of data transfer that sequentially accumulate a plurality of data granules for transfer in association with a single addressIBM·Filed 2000·Granted Feb 17, 2004·10 cites·16 claims
- 3260US7581084B2Method and apparatus for efficient loading and storing of vectorsNINTENDO CO LTD·Filed 2004·Granted Aug 25, 2009·5 cites·25 claims
- 3359US8397189B2Model checking in state transition machine verificationPARUTHI VIRESH·Filed 2011·Granted Mar 12, 2013·1 cites·20 claims
- 3457US7865749B2Method and apparatus for dynamic system-level frequency scalingIBM·Filed 2003·Granted Jan 4, 2011·5 cites·18 claims
- 3556US10824952B2Reconfigurable array processor for pattern matchingIBM·Filed 2014·Granted Nov 3, 2020·0 cites·20 claims
- 3651US9189380B2Systems and methods to save and restore a write gather pipeIBM·Filed 2013·Granted Nov 17, 2015·0 cites·20 claims
- 3750US10824953B2Reconfigurable array processor for pattern matchingIBM·Filed 2015·Granted Nov 3, 2020·0 cites·20 claims
- 3850US8019970B2Three-dimensional networking design structureIBM·Filed 2007·Granted Sep 13, 2011·0 cites·15 claims
- 3950US6591361B1Method and apparatus for converting data into different ordinal typesIBM·Filed 1999·Granted Jul 8, 2003·21 cites·26 claims
- 4049US11907361B2System and method for supporting secure objects using a memory access control monitorIBM·Filed 2020·Granted Feb 20, 2024·0 cites·19 claims
- 4148US2009094566A1Design structure for chip identification systemIBM·Filed 2008·Application pending·0 cites
- 4248US2009132747A1Structure for universal peripheral processor system for soc environments on an integrated circuitIBM·Filed 2008·Application pending·0 cites
- 4348US2009144504A1STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONSIBM·Filed 2008·Application pending·0 cites
- 4447US2009144507A1APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONSIBM·Filed 2007·Application pending·0 cites
- 4547US2008278195A1Structure for executing software within real-time hardware constraints using functionally programmable branch tableIBM·Filed 2008·Application pending·0 cites
- 4647US2009132732A1Universal peripheral processor system for soc environments on an integrated circuitIBM·Filed 2007·Application pending·0 cites
- 4746US2006064606A1A method and apparatus for controlling power consumption in an integrated circuitIBM·Filed 2004·Application pending·0 cites
- 4845US7865694B2Three-dimensional networking structureIBM·Filed 2006·Granted Jan 4, 2011·0 cites·12 claims
- 4945US2008183941A1Hardware assisted bus state transition using content addressable memories.IBM·Filed 2007·Application pending·0 cites
- 5044US2004225868A1An integrated circuit having parallel execution units with differing execution latenciesIBM·Filed 2003·Application pending·0 cites
Showing the top 50 of 58 patent records by PatentIndex Score.
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