Inventor · disambiguated record
Michael D. Snyder
Also filed as: SNYDER MICHAEL · SNYDER MICHAEL D · SNYDER MICHAEL DEAN
50 granted patents·9 pending applications·1,152 citations·filing 1978–2025
98Inventor score
Top patents by PatentIndex Score
59 records- 0190US8261047B2Qualification of conditional debug instructions based on addressMOYER WILLIAM C·Filed 2008·Granted Sep 4, 2012·22 cites·20 claims
- 0289US8615644B2Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource conditionBRUCE BECKY·Filed 2010·Granted Dec 24, 2013·18 cites·13 claims
- 0389US6073215AData processing system having a data prefetch mechanism and method thereforMOTOROLA INC·Filed 1998·Granted Jun 6, 2000·161 cites·11 claims
- 0488US6202130B1Data processing system for processing vector data and method thereforMOTOROLA INC·Filed 1998·Granted Mar 13, 2001·162 cites·29 claims
- 0587US6785772B2Data prefetching apparatus in a data processing system and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Aug 31, 2004·47 cites·21 claims
- 0686US7681021B2Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branchFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 16, 2010·19 cites·10 claims
- 0786US4193064AMultiple pulse timerSNYDER MICHAEL D·Filed 1978·Granted Mar 11, 1980·37 cites·11 claims
- 0885US7852692B2Memory operation testingFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Dec 14, 2010·17 cites·20 claims
- 0985US6119203AMechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing systemMOTOROLA INC·Filed 1998·Granted Sep 12, 2000·129 cites·14 claims
- 1084US9047079B2Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource conditionBRUCE BECKY·Filed 2012·Granted Jun 2, 2015·10 cites·7 claims
- 1183US7506105B2Prefetching using hashed program counterFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 17, 2009·19 cites·25 claims
- 1282US8156357B2Voltage-based memory size scaling in a data processing systemZHANG SHAYAN·Filed 2009·Granted Apr 10, 2012·12 cites·20 claims
- 1382US7849247B2Interrupt controller for accelerated interrupt handling in a data processing system and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Dec 7, 2010·11 cites·18 claims
- 1482US6581140B1Method and apparatus for improving access time in set-associative cache systemsMOTOROLA INC·Filed 2000·Granted Jun 17, 2003·41 cites·20 claims
- 1581US8117618B2Forward progress mechanism for a multithreaded processorHOLLOWAY DAVID C·Filed 2007·Granted Feb 14, 2012·16 cites·20 claims
- 1679US12299447B2Hardware verification of dynamically generated codeAPPLE INC·Filed 2023·Granted May 13, 2025·0 cites·20 claims
- 1779US8531899B2Methods for testing a memory embedded in an integrated circuitZHANG SHAYAN·Filed 2012·Granted Sep 10, 2013·6 cites·11 claims
- 1879US2025258673A1Hardware Verification of Dynamically Generated CodeAPPLE INC·Filed 2025·Application pending·0 cites
- 1978US8379466B2Integrated circuit having an embedded memory and method for testing the memoryFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Feb 19, 2013·10 cites·12 claims
- 2078US8041901B2Performance monitoring device and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Oct 18, 2011·8 cites·20 claims
- 2177US7827360B2Cache locking device and methods thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 2, 2010·11 cites·20 claims
- 2277US6269427B1Multiple load miss handling in a cache memory systemIBM·Filed 1999·Granted Jul 31, 2001·77 cites·20 claims
- 2377US5630095AMethod for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system thereforMOTOROLA INC·Filed 1995·Granted May 13, 1997·81 cites·2 claims
- 2472US7941499B2Interprocessor message transmission via coherency-based interconnectFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 10, 2011·6 cites·20 claims
- 2571US8539485B2Polling using reservation mechanismSNYDER MICHAEL D·Filed 2007·Granted Sep 17, 2013·6 cites·17 claims
- 2671US7689815B2Debug instruction for use in a data processing systemFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 30, 2010·5 cites·14 claims
- 2770US11816484B2Hardware verification of dynamically generated codeAPPLE INC·Filed 2021·Granted Nov 14, 2023·0 cites·17 claims
- 2869US8380779B2Technique for determining if a logical sum of a first operand and a second operand is the same as a third operandFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Feb 19, 2013·4 cites·17 claims
- 2967US7688656B2Integrated circuit memory having dynamically adjustable read margin and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 30, 2010·6 cites·21 claims
- 3067US7675806B2Low voltage memory device and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 9, 2010·7 cites·18 claims
- 3166US8122437B2Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processorsXU ZHENG·Filed 2008·Granted Feb 21, 2012·4 cites·19 claims
- 3266US7069384B2System and method for cache external writing and write shadowingFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 27, 2006·10 cites·15 claims
- 3366US6499116B1Performance of data stream touch eventsIBM·Filed 1999·Granted Dec 24, 2002·48 cites·39 claims
- 3465US6842822B2System and method for cache external writingFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Jan 11, 2005·10 cites·20 claims
- 3563US9026742B2System and method for processing potentially self-inconsistent memory transactionsDESHPANDE SANJAY R·Filed 2007·Granted May 5, 2015·3 cites·20 claims
- 3663US8990633B2Tracing support for interconnect fabricXU ZHENG·Filed 2009·Granted Mar 24, 2015·2 cites·23 claims
- 3763US8627471B2Permissions checking for data processing instructionsMOYER WILLIAM C·Filed 2008·Granted Jan 7, 2014·2 cites·21 claims
- 3862US9213665B2Data processor for processing a decorated storage notifyMOYER WILLIAM C·Filed 2008·Granted Dec 15, 2015·2 cites·22 claims
- 3960US6163835AMethod and apparatus for transferring data over a processor interface busMOTOROLA INC·Filed 1998·Granted Dec 19, 2000·38 cites·23 claims
- 4057US6240479B1Method and apparatus for transferring data on a split bus in a data processing systemMOTOROLA INC·Filed 1998·Granted May 29, 2001·32 cites·4 claims
- 4156US8832702B2Thread de-emphasis instruction for multithreaded processorBRUCE KLAS M·Filed 2007·Granted Sep 9, 2014·2 cites·20 claims
- 4254US11893413B2Virtual channel support using write tableAPPLE INC·Filed 2021·Granted Feb 6, 2024·0 cites·20 claims
- 4354US2025209160A1Processor Instruction for Secure Pointer ArithmeticAPPLE INC·Filed 2024·Application pending·0 cites
- 4453US8199547B2Error detection in a content addressable memory (CAM)RAMARAJU RAVINDRARAJ·Filed 2010·Granted Jun 12, 2012·1 cites·20 claims
- 4553US2025094355A1Translation Lookaside Buffer Entry LockingAPPLE INC·Filed 2023·Application pending·0 cites
- 4652US7941646B2Completion continue on thread switch based on instruction progress metric mechanism for a microprocessorFREESCALE SEMICONDOCTOR INC·Filed 2007·Granted May 10, 2011·1 cites·20 claims
- 4751US9395983B2Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operationMOYER WILLIAM C·Filed 2008·Granted Jul 19, 2016·0 cites·24 claims
- 4851US5422914ASystem and method for synchronizing data communications between two devices operating at different clock frequenciesMOTOROLA INC·Filed 1993·Granted Jun 6, 1995·23 cites·12 claims
- 4949US6321303B1Dynamically modifying queued transactions in a cache memory systemIBM·Filed 1999·Granted Nov 20, 2001·22 cites·20 claims
- 5048US8972671B2Method and apparatus for cache transactions in a data processing systemMOYER WILLIAM C·Filed 2007·Granted Mar 3, 2015·0 cites·16 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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